diff --git a/artiq/gateware/rtio/cri.py b/artiq/gateware/rtio/cri.py
index 1d2b89435..2a871f736 100644
--- a/artiq/gateware/rtio/cri.py
+++ b/artiq/gateware/rtio/cri.py
@@ -6,6 +6,11 @@ from migen.genlib.record import *
 from misoc.interconnect.csr import *
 
 
+# CRI write happens in 3 cycles:
+# 1. set timestamp and channel
+# 2. set other payload elements and issue write command
+# 3. check status
+
 commands = {
     "nop": 0,
 
diff --git a/artiq/gateware/rtio/sed/lane_distributor.py b/artiq/gateware/rtio/sed/lane_distributor.py
index a2834f13b..4f8b7e146 100644
--- a/artiq/gateware/rtio/sed/lane_distributor.py
+++ b/artiq/gateware/rtio/sed/lane_distributor.py
@@ -7,11 +7,6 @@ from artiq.gateware.rtio.sed import layouts
 __all__ = ["LaneDistributor"]
 
 
-# CRI write happens in 3 cycles:
-# 1. set timestamp and channel
-# 2. set other payload elements and issue write command
-# 3. check status
-
 class LaneDistributor(Module):
     def __init__(self, lane_count, seqn_width, layout_payload,
                  compensation, glbl_fine_ts_width,