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serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue... 

rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)
This commit is contained in:
Florent Kermarrec 2017-11-18 18:01:46 +01:00
parent 1b976bfa4d
commit f003566e52
1 changed files with 4 additions and 2 deletions
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6
artiq/gateware/serwb/phy.py
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@ -37,6 +37,8 @@ class _SerdesMasterInit(Module):
self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE")) self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
self.comb += self.fsm.reset.eq(self.reset) self.comb += self.fsm.reset.eq(self.reset)
self.comb += serdes.rx_delay_inc.eq(1)
fsm.act("IDLE", fsm.act("IDLE",
NextValue(delay, 0), NextValue(delay, 0),
NextValue(delay_min, 0), NextValue(delay_min, 0),
@ -107,7 +109,6 @@ class _SerdesMasterInit(Module):
serdes.rx_delay_rst.eq(1) serdes.rx_delay_rst.eq(1)
).Else( ).Else(
NextValue(delay, delay + 1), NextValue(delay, delay + 1),
serdes.rx_delay_inc.eq(1),
serdes.rx_delay_ce.eq(1) serdes.rx_delay_ce.eq(1)
), ),
serdes.tx_comma.eq(1) serdes.tx_comma.eq(1)
@ -171,6 +172,8 @@ class _SerdesSlaveInit(Module, AutoCSR):
self.comb += self.reset.eq(serdes.rx_idle) self.comb += self.reset.eq(serdes.rx_idle)
self.comb += serdes.rx_delay_inc.eq(1)
self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE")) self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
fsm.act("IDLE", fsm.act("IDLE",
NextValue(delay, 0), NextValue(delay, 0),
@ -228,7 +231,6 @@ class _SerdesSlaveInit(Module, AutoCSR):
serdes.rx_delay_rst.eq(1) serdes.rx_delay_rst.eq(1)
).Else( ).Else(
NextValue(delay, delay + 1), NextValue(delay, delay + 1),
serdes.rx_delay_inc.eq(1),
serdes.rx_delay_ce.eq(1) serdes.rx_delay_ce.eq(1)
), ),
serdes.tx_idle.eq(1) serdes.tx_idle.eq(1)