From f003566e525680db47eb29a48a53a8e09e0d8785 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 18 Nov 2017 18:01:46 +0100 Subject: [PATCH] serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue... rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer) --- artiq/gateware/serwb/phy.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/serwb/phy.py b/artiq/gateware/serwb/phy.py index eb1050c66..d48084116 100644 --- a/artiq/gateware/serwb/phy.py +++ b/artiq/gateware/serwb/phy.py @@ -37,6 +37,8 @@ class _SerdesMasterInit(Module): self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE")) self.comb += self.fsm.reset.eq(self.reset) + self.comb += serdes.rx_delay_inc.eq(1) + fsm.act("IDLE", NextValue(delay, 0), NextValue(delay_min, 0), @@ -107,7 +109,6 @@ class _SerdesMasterInit(Module): serdes.rx_delay_rst.eq(1) ).Else( NextValue(delay, delay + 1), - serdes.rx_delay_inc.eq(1), serdes.rx_delay_ce.eq(1) ), serdes.tx_comma.eq(1) @@ -171,6 +172,8 @@ class _SerdesSlaveInit(Module, AutoCSR): self.comb += self.reset.eq(serdes.rx_idle) + self.comb += serdes.rx_delay_inc.eq(1) + self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE")) fsm.act("IDLE", NextValue(delay, 0), @@ -228,7 +231,6 @@ class _SerdesSlaveInit(Module, AutoCSR): serdes.rx_delay_rst.eq(1) ).Else( NextValue(delay, delay + 1), - serdes.rx_delay_inc.eq(1), serdes.rx_delay_ce.eq(1) ), serdes.tx_idle.eq(1)