forked from M-Labs/artiq
serwb: fix rx_delay_inc on ultrascale, this was the issue serwb issue...
rx_delay_inc and rx_delay_ce were set for only one cycle, on ultrascale, these signals are translated to serwb_serdes_5x clock domain and we now set rx_delay_inc always to 1 (MultiReg), rx_delay_ce for one cycle (PulseSynchronizer)
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1b976bfa4d
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f003566e52
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@ -37,6 +37,8 @@ class _SerdesMasterInit(Module):
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
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self.comb += self.fsm.reset.eq(self.reset)
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self.comb += serdes.rx_delay_inc.eq(1)
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fsm.act("IDLE",
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NextValue(delay, 0),
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NextValue(delay_min, 0),
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@ -107,7 +109,6 @@ class _SerdesMasterInit(Module):
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serdes.rx_delay_rst.eq(1)
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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serdes.rx_delay_ce.eq(1)
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),
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serdes.tx_comma.eq(1)
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@ -171,6 +172,8 @@ class _SerdesSlaveInit(Module, AutoCSR):
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self.comb += self.reset.eq(serdes.rx_idle)
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self.comb += serdes.rx_delay_inc.eq(1)
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
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fsm.act("IDLE",
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NextValue(delay, 0),
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@ -228,7 +231,6 @@ class _SerdesSlaveInit(Module, AutoCSR):
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serdes.rx_delay_rst.eq(1)
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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serdes.rx_delay_ce.eq(1)
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),
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serdes.tx_idle.eq(1)
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