srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

Revert "drtio: monitor RTIOClockMultiplier PLL (#1155)" 

This reverts commit 469a66db61.
This commit is contained in:
Sebastien Bourdeauducq 2018-11-07 22:01:03 +08:00
parent 73b7124091
commit efd735a6ab
3 changed files with 6 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
artiq/firmware/runtime/rtio_mgt.rs
View File

@ -257,10 +257,6 @@ fn async_error_thread(io: Io) {
}
pub fn startup(io: &Io) {
// The RTIO CRG may depend on the DRTIO transceiver clock.
// Initialize DRTIO first to bring up transceiver clocking.
drtio::startup(io);
#[cfg(has_rtio_crg)]
{
#[cfg(has_rtio_clock_switch)]
@ -300,6 +296,7 @@ pub fn startup(io: &Io) {
}
}
drtio::startup(io);
init_core(true);
io.spawn(4096, async_error_thread);
}

18
artiq/firmware/satman/main.rs
View File

@ -229,23 +229,6 @@ fn process_errors() {
}
}
#[cfg(has_rtio_crg)]
fn init_rtio_crg() {
unsafe {
csr::rtio_crg::pll_reset_write(0);
}
clock::spin_us(150);
let locked = unsafe { csr::rtio_crg::pll_locked_read() != 0 };
if !locked {
error!("RTIO clock failed");
}
}
#[cfg(not(has_rtio_crg))]
fn init_rtio_crg() { }
#[cfg(rtio_frequency = "150.0")]
const SI5324_SETTINGS: si5324::FrequencySettings
= si5324::FrequencySettings {
@ -302,7 +285,6 @@ pub extern fn main() -> i32 {
unsafe {
csr::drtio_transceiver::stable_clkin_write(1);
}
init_rtio_crg();
#[cfg(has_allaki_atts)]
board_artiq::hmc542::program_all(8/*=4dB*/);

18
artiq/gateware/targets/kasli.py
View File

@ -766,23 +766,19 @@ class Tester(_StandaloneBase):
self.rtio_crg.cd_rtio.clk, self.grabber0.deserializer.cd_cl.clk)
class _RTIOClockMultiplier(Module, AutoCSR):
class _RTIOClockMultiplier(Module):
def __init__(self, rtio_clk_freq):
self.pll_reset = CSRStorage(reset=1)
self.pll_locked = CSRStatus()
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
# See "Global Clock Network Deskew Using Two BUFGs" in ug472.
clkfbout = Signal()
clkfbin = Signal()
rtiox4_clk = Signal()
pll_locked = Signal()
self.specials += [
Instance("MMCME2_BASE",
p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
i_CLKIN1=ClockSignal("rtio"),
i_RST=self.pll_reset.storage,
o_LOCKED=pll_locked,
i_RST=ResetSignal("rtio"),
p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
@ -791,9 +787,7 @@ class _RTIOClockMultiplier(Module, AutoCSR):
p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
),
Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
MultiReg(pll_locked, self.pll_locked.status)
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk)
]
@ -877,8 +871,7 @@ class _MasterBase(MiniSoC, AMPSoC):
platform.add_false_path_constraints(
self.crg.cd_sys.clk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
fix_serdes_timing_path(platform)
def add_rtio(self, rtio_channels):
@ -1003,8 +996,7 @@ class _SatelliteBase(BaseSoC):
self.crg.cd_sys.clk,
gtp.txoutclk, gtp.rxoutclk)
self.submodules.rtio_crg = _RTIOClockMultiplier(rtio_clk_freq)
self.csr_devices.append("rtio_crg")
self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
fix_serdes_timing_path(platform)
def add_rtio(self, rtio_channels):