forked from M-Labs/artiq
Merge branch 'shrink-dds-wb'
* shrink-dds-wb: ad9858: make wb data 8 bit wide
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commit
ef96de7d26
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@ -38,7 +38,7 @@ class AD9858(Module):
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read_wait_cycles=10, hiz_wait_cycles=3,
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bus=None):
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if bus is None:
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bus = wishbone.Interface()
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bus = wishbone.Interface(data_width=8)
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self.bus = bus
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# # #
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