From 45ec5dbe84872e340115cb4a9764f2826e37d389 Mon Sep 17 00:00:00 2001
From: Robert Jordens <jordens@gmail.com>
Date: Sat, 20 Jun 2015 23:33:55 -0600
Subject: [PATCH] ad9858: make wb data 8 bit wide

matches actual dds bus data width and saves bram
---
 artiq/gateware/ad9858.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/gateware/ad9858.py b/artiq/gateware/ad9858.py
index d620cac43..5b475d628 100644
--- a/artiq/gateware/ad9858.py
+++ b/artiq/gateware/ad9858.py
@@ -38,7 +38,7 @@ class AD9858(Module):
                  read_wait_cycles=10, hiz_wait_cycles=3,
                  bus=None):
         if bus is None:
-            bus = wishbone.Interface()
+            bus = wishbone.Interface(data_width=8)
         self.bus = bus
 
         # # #