From ede3667fd3539b5ca1fba76853cdb0647d3fcb3b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 20 Jul 2014 18:38:41 -0600 Subject: [PATCH] soc/target: use only 8 TTL channels for now --- soc/targets/artiq.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py index 511c7822e..9c832c225 100644 --- a/soc/targets/artiq.py +++ b/soc/targets/artiq.py @@ -104,6 +104,6 @@ class ARTIQSoC(SDRAMSoC): self.register_rom(self.spiflash.bus) self.submodules.leds = gpio.GPIOOut(platform.request("user_led")) - self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(16)]) + self.submodules.rtio = rtio.RTIO([platform.request("ttl", i) for i in range(8)]) default_subtarget = ARTIQSoC