dsp.accu: reset_less outputs

2017-06-28 20:04:58 +02:00 · 2017-06-28 20:04:58 +02:00 · e7db2c6578
parent 6bb994228f
commit e7db2c6578
1 changed files with 2 additions and 0 deletions
--- a/artiq/gateware/dsp/accu.py
+++ b/artiq/gateware/dsp/accu.py
@ -76,6 +76,8 @@ class PhasedAccu(Module):
        self.submodules += a
        z = [Signal(width) for i in range(parallelism)]
        o = self.o.payload.flatten()
+        for oi in o:
+            oi.reset_less = True
        load = Signal()
        clr = Signal()
        p = Signal.like(self.i.p)