diff --git a/artiq/gateware/dsp/accu.py b/artiq/gateware/dsp/accu.py
index 6e8776476..9e583b110 100644
--- a/artiq/gateware/dsp/accu.py
+++ b/artiq/gateware/dsp/accu.py
@@ -76,6 +76,8 @@ class PhasedAccu(Module):
         self.submodules += a
         z = [Signal(width) for i in range(parallelism)]
         o = self.o.payload.flatten()
+        for oi in o:
+            oi.reset_less = True
         load = Signal()
         clr = Signal()
         p = Signal.like(self.i.p)