forked from M-Labs/artiq
dsp.accu: reset_less outputs
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@ -76,6 +76,8 @@ class PhasedAccu(Module):
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self.submodules += a
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z = [Signal(width) for i in range(parallelism)]
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o = self.o.payload.flatten()
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for oi in o:
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oi.reset_less = True
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load = Signal()
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clr = Signal()
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p = Signal.like(self.i.p)
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