forked from M-Labs/artiq
dsp.accu: reset_less outputs
This commit is contained in:
parent
6bb994228f
commit
e7db2c6578
@ -76,6 +76,8 @@ class PhasedAccu(Module):
|
||||
self.submodules += a
|
||||
z = [Signal(width) for i in range(parallelism)]
|
||||
o = self.o.payload.flatten()
|
||||
for oi in o:
|
||||
oi.reset_less = True
|
||||
load = Signal()
|
||||
clr = Signal()
|
||||
p = Signal.like(self.i.p)
|
||||
|
Loading…
Reference in New Issue
Block a user