forked from M-Labs/artiq
gateware.spi: design sketch
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from migen import *
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from artiq.gateware.spi import SPIMaster as SPIMasterWB
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from artiq.gateware.rtio.phy.wishbone import RT2WB
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class SPIMaster(Module):
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def __init__(self, pads, onehot=False, **kwargs):
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self.submodules._ll = ClockDomainsRenamer("rio")(
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SPIMasterWB(pads, **kwargs))
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self.submodules._rt2wb = RT2WB(2, self._ll.bus)
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self.rtlink = self._rt2wb.rtlink
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self.probes = []
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect import wishbone
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class SPIMaster(Module):
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"""SPI Master.
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Notes:
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* If there is a miso wire in pads, the input and output are done with
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two signals (a.k.a. 4-wire SPI), else mosi is used for both output
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and input (a.k.a. 3-wire SPI).
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* Every transfer consists of a 0-32 bit write followed by a 0-32
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bit read.
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* cs_n is always asserted at the beginning and deasserted
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at the end of the tranfer.
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* cs_n handling is agnostic to whether it is one-hot or decoded
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somewhere downstream. If it is decoded, "cs_n all deasserted"
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should be handled accordingly (no slave selected).
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If it is one-hot, asserting multiple slaves should only be attempted
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if miso is either not connected between slaves or open collector.
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* If config.cs_polarity == 0 (cs active low, the default),
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"cs_n all deasserted" means "all cs_n bits high".
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* The first bit output on mosi is always the MSB/LSB (depending on
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config.lsb_first) of the data register, independent of
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xfer.write_len. The last bit input from miso always ends up in
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the LSB/MSB (respectively) of the data register, independent of
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read_len.
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* For 4-wire SPI only the sum of read_len and write_len matters. The
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behavior is the same no matter how the transfer length is divided
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between the two. For 3-wire SPI, the direction of mosi/miso is
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switched from output to input after write_len cycles, at the
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"output" clk edge corresponding to bit write_len + 1 of the transfer.
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* Data output on mosi in 4-wire SPI during the read cycles is
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undefined. Data in the data register outside the
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least/most (depending on config.lsb_first) significant read_len
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bits is undefined.
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* The transfer is complete when the wishbone transaction is ack-ed.
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* Input data from the last transaction can be read from the data
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register at any time.
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Transaction Sequence:
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* if desired, write the xfer register to change lengths and cs_n.
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* write the data register (also for zero-length writes),
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writing triggers the transfer and the transfer is complete when the
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write is complete.
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* if desired, read the data register
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Register address and bit map:
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config (address 0):
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1 offline: all pins high-z (reset=1)
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1 cs_polarity: active level of chip select (reset=0)
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1 clk_polarity: idle level for clk (reset=0)
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1 clk_phase: first edge after cs assertion to sample data on (reset=0)
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(0, 0): idle low, output on falling, input on rising
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(0, 1): idle low, output on rising, input on falling
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(1, 0): idle high, output on rising, input on falling
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(1, 1): idle high, output on falling, input on rising
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1 lsb_first: LSB is the first bit on the wire (reset=0)
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11 undefined
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16 speed: divider from this module's clock to the SPI clk
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(minimum=2, reset=4)
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clk pulses are asymmetric if speed is odd, favoring longer setup
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over hold times
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xfer (address 1):
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16 cs: active high bit mask of chip selects to assert
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6 write_len: 0-32 bits
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2 undefined
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6 read_len: 0-32 bits
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2 undefined
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data (address 2):
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32 write/read data
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"""
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def __init__(self, pads, bus=None):
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if bus is None:
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bus = wishbone.Interface(data_width=32)
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self.bus = bus
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###
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def _test_gen(bus):
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yield from bus.write(0, 0 | (5 << 16))
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yield
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yield from bus.write(1, 1 | (24 << 16) | (16 << 24))
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yield
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yield from bus.write(2, 0x12345678)
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yield
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r = (yield from bus.read(2))
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print(r)
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yield
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class _TestPads:
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def __init__(self):
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self.cs_n = Signal(3)
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self.clk = Signal()
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self.mosi = Signal()
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self.miso = Signal()
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if __name__ == "__main__":
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pads = _TestPads()
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dut = SPIMaster(pads)
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run_simulation(dut, _test_gen(dut.bus), vcd_name="spi_master.vcd")
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