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gateware/spi: stubs

This commit is contained in:
Robert Jördens 2016-02-26 13:11:10 +01:00
parent 82a8e819ac
commit fb929c8599
1 changed files with 18 additions and 4 deletions
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22
artiq/gateware/targets/pipistrello.py
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@ -19,7 +19,7 @@ from misoc.targets.pipistrello import *
from artiq.gateware.soc import AMPSoC
from artiq.gateware import rtio, nist_qc1
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi
from artiq import __artiq_dir__ as artiq_dir
from artiq import __version__ as artiq_version
@ -152,12 +152,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
ofifo_depth=4))
# ttl2 can run on a 8x serdes if xtrig is not used
for i in range(15):
# the last five ttls are used for SPI and a ClockGen
for i in range(11):
if i in (0, 1):
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
self.rtio_crg.rtiox4_stb)
elif i in (2,):
elif i in (2,): # ttl2 can run on a 8x serdes if xtrig is not used
phy = ttl_serdes_spartan6.Output_8X(platform.request("ttl", i),
self.rtio_crg.rtiox8_stb)
else:
@ -192,6 +192,20 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
ofifo_depth=512,
ififo_depth=4))
spi_pins = Record([("cs_n", 1), ("clk", 1), ("mosi", 1), ("miso", 1)])
# cs_n can be multiple bits wide, one-hot
# absence of miso indicates bidirectional mosi
self.comb += [
platform.request("ttl", 11).eq(spi_pins.cs_n),
platform.request("ttl", 12).eq(spi_pins.clk),
platform.request("ttl", 13).eq(spi_pins.mosi),
spi_pins.miso.eq(platform.request("ttl", 14)),
]
phy = spi.SPIMaster(spi_pins)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
rtio_channels.append(rtio.LogChannel())