forked from M-Labs/artiq
wrpll: fix run signal
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8dd9a6d024
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@ -115,7 +115,7 @@ class I2CMasterMachine(Module):
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run = Signal()
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idle = Signal()
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self.comb += [
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run.eq(self.start | self.stop | self.write),
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run.eq((self.start | self.stop | self.write) & self.ready),
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idle.eq(~run & fsm.ongoing("IDLE")),
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self.cg.ce.eq(~idle),
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fsm.ce.eq(run | self.cg.clk2x),
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