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suservo/adc: try to help vivado extract srls

This commit is contained in:
Robert Jördens 2018-04-23 18:21:03 +00:00
parent 929ed4471b
commit e36deab0a8
1 changed files with 5 additions and 3 deletions
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8
artiq/gateware/suservo/adc_ser.py
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@ -126,16 +126,18 @@ class ADC(Module, DiffMixin):
k = p.channels//p.lanes k = p.channels//p.lanes
assert 2*t_read == k*p.width assert 2*t_read == k*p.width
for i, sdo in enumerate(sdo): for i, sdo in enumerate(sdo):
sdo_sr = Signal(2*t_read - 2) sdo_sr0 = Signal(t_read - 1)
sdo_sr1 = Signal(t_read - 1)
sdo_ddr = Signal(2) sdo_ddr = Signal(2)
self.specials += io.DDRInput(sdo, sdo_ddr[1], sdo_ddr[0], self.specials += io.DDRInput(sdo, sdo_ddr[1], sdo_ddr[0],
self.cd_ret.clk) self.cd_ret.clk)
self.sync.ret += [ self.sync.ret += [
If(self.reading & sck_en_ret, If(self.reading & sck_en_ret,
sdo_sr.eq(Cat(sdo_ddr, sdo_sr)) sdo_sr0.eq(Cat(sdo_ddr[0], sdo_sr0)),
sdo_sr1.eq(Cat(sdo_ddr[1], sdo_sr1))
) )
] ]
self.comb += [ self.comb += [
Cat(reversed([self.data[i*k + j] for j in range(k)])).eq( Cat(reversed([self.data[i*k + j] for j in range(k)])).eq(
Cat(sdo_ddr, sdo_sr)) Cat(sdo_ddr, zip(sdo_sr0, sdo_sr1)))
] ]