forked from M-Labs/artiq
parent
4c1e356f67
commit
929ed4471b
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@ -19,7 +19,9 @@ from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.amp import AMPSoC
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, spi2
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from artiq.gateware.rtio.phy import (
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ttl_simple, ttl_serdes_7series, spi2, servo as rtservo)
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from artiq.gateware.suservo import servo, pads as servo_pads
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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@ -328,6 +330,59 @@ def _urukul(eem, eem_aux=None):
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return ios
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def _urukul_qspi(eem0, eem1):
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ios = [
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("{}_spi_p".format(eem0), 0,
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Subsignal("clk", Pins(_eem_pin(eem0, 0, "p"))),
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Subsignal("mosi", Pins(_eem_pin(eem0, 1, "p"))),
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Subsignal("cs_n", Pins(
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_eem_pin(eem0, 3, "p"), _eem_pin(eem0, 4, "p"))),
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IOStandard("LVDS_25"),
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),
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("{}_spi_n".format(eem0), 0,
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Subsignal("clk", Pins(_eem_pin(eem0, 0, "n"))),
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Subsignal("mosi", Pins(_eem_pin(eem0, 1, "n"))),
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Subsignal("cs_n", Pins(
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_eem_pin(eem0, 3, "n"), _eem_pin(eem0, 4, "n"))),
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IOStandard("LVDS_25"),
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),
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]
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ttls = [(6, eem0, "io_update"),
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(7, eem0, "dds_reset"),
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(4, eem1, "sw0"),
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(5, eem1, "sw1"),
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(6, eem1, "sw2"),
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(7, eem1, "sw3")]
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for i, j, sig in ttls:
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ios.append(
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("{}_{}".format(eem0, sig), 0,
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Subsignal("p", Pins(_eem_pin(j, i, "p"))),
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Subsignal("n", Pins(_eem_pin(j, i, "n"))),
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IOStandard("LVDS_25")
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))
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ios += [
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("{}_qspi_p".format(eem0), 0,
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Subsignal("cs_n", Pins(_eem_pin(eem0, 5, "p"))),
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Subsignal("clk", Pins(_eem_pin(eem0, 2, "p"))),
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Subsignal("mosi0", Pins(_eem_pin(eem1, 0, "p"))),
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Subsignal("mosi1", Pins(_eem_pin(eem1, 1, "p"))),
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Subsignal("mosi2", Pins(_eem_pin(eem1, 2, "p"))),
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Subsignal("mosi3", Pins(_eem_pin(eem1, 3, "p"))),
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IOStandard("LVDS_25"),
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),
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("{}_qspi_n".format(eem0), 0,
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Subsignal("cs_n", Pins(_eem_pin(eem0, 5, "n"))),
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Subsignal("clk", Pins(_eem_pin(eem0, 2, "n"))),
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Subsignal("mosi0", Pins(_eem_pin(eem1, 0, "n"))),
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Subsignal("mosi1", Pins(_eem_pin(eem1, 1, "n"))),
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Subsignal("mosi2", Pins(_eem_pin(eem1, 2, "n"))),
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Subsignal("mosi3", Pins(_eem_pin(eem1, 3, "n"))),
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IOStandard("LVDS_25"),
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),
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]
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return ios
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class Opticlock(_StandaloneBase):
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"""
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Opticlock extension variant configuration
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@ -448,8 +503,8 @@ class SUServo(_StandaloneBase):
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platform.add_extension(_dio("eem0"))
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platform.add_extension(_dio("eem1"))
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platform.add_extension(_sampler("eem3", "eem2"))
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platform.add_extension(_urukul("eem5", "eem4"))
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platform.add_extension(_urukul("eem7", "eem6"))
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platform.add_extension(_urukul_qspi("eem5", "eem4"))
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platform.add_extension(_urukul_qspi("eem7", "eem6"))
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try:
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# EEM clock fan-out from Si5324, not MMCX, only Kasli/v1.0
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@ -470,23 +525,27 @@ class SUServo(_StandaloneBase):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# EEM3, EEM2: Sampler
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phy = spi2.SPIMaster(self.platform.request("eem3_adc_spi_p"),
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self.platform.request("eem3_adc_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=16))
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phy = spi2.SPIMaster(self.platform.request("eem3_pgia_spi_p"),
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self.platform.request("eem3_pgia_spi_n"))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=2))
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sampler_pads = servo_pads.SamplerPads(self.platform, "eem3", "eem2")
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# EEM5, EEM4 and EEM7, EEM6: Urukul
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urukul_pads = servo_pads.UrukulPads(self.platform,
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"eem5", "eem4", "eem7", "eem6")
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adc_p = servo.ADCParams(width=16, channels=8, lanes=4,
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t_cnvh=4, t_conv=57, t_rtt=4)
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iir_p = servo.IIRWidths(state=25, coeff=18, adc=16,
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asf=14, word=16, accu=48, shift=11,
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channel=3, profile=5)
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dds_p = servo.DDSParams(width=8 + 32 + 16 + 16,
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channels=adc_p.channels, clk=1)
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su = servo.Servo(sampler_pads, urukul_pads, adc_p, iir_p, dds_p)
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su = ClockDomainsRenamer({"sys": "rio_phy"})(su)
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self.submodules += sampler_pads, urukul_pads, su
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for signal in "cnv".split():
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pads = platform.request("eem3_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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pads = platform.request("eem3_sdr")
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self.specials += DifferentialOutput(1, pads.p, pads.n)
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ctrls = [rtservo.RTServoCtrl(ctrl) for ctrl in su.iir.ctrl]
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self.submodules += ctrls
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rtio_channels.extend(rtio.Channel.from_phy(ctrl) for ctrl in ctrls)
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mem = rtservo.RTServoMem(iir_p, su.iir)
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self.submodules += mem
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rtio_channels.append(rtio.Channel.from_phy(mem, ififo_depth=4))
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# EEM5 + EEM4: Urukul
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phy = spi2.SPIMaster(self.platform.request("eem5_spi_p"),
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@ -497,11 +556,11 @@ class SUServo(_StandaloneBase):
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pads = platform.request("eem5_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for signal in "io_update sw0 sw1 sw2 sw3".split():
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for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
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pads = platform.request("eem5_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.specials += DifferentialOutput(
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su.iir.ctrl[i].en_out,
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pads.p, pads.n)
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# EEM7 + EEM6: Urukul
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phy = spi2.SPIMaster(self.platform.request("eem7_spi_p"),
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@ -512,11 +571,11 @@ class SUServo(_StandaloneBase):
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pads = platform.request("eem7_dds_reset")
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self.specials += DifferentialOutput(0, pads.p, pads.n)
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for signal in "io_update sw0 sw1 sw2 sw3".split():
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for i, signal in enumerate("sw0 sw1 sw2 sw3".split()):
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pads = platform.request("eem7_{}".format(signal))
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.specials += DifferentialOutput(
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su.iir.ctrl[i + 4].en_out,
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pads.p, pads.n)
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for i in (1, 2):
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sfp_ctl = platform.request("sfp_ctl", i)
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@ -530,6 +589,14 @@ class SUServo(_StandaloneBase):
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self.add_rtio(rtio_channels)
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platform.add_period_constraint(su.adc.cd_ret.clk, 8.)
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platform.add_false_path_constraints(
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su.adc.cd_ret.clk,
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self.rtio_crg.cd_rtio.clk)
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platform.add_false_path_constraints(
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su.adc.cd_ret.clk,
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self.crg.cd_sys.clk)
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class SYSU(_StandaloneBase):
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def __init__(self, **kwargs):
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