forked from M-Labs/artiq
suservo/adc: try to help vivado extract srls
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@ -126,16 +126,18 @@ class ADC(Module, DiffMixin):
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k = p.channels//p.lanes
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assert 2*t_read == k*p.width
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for i, sdo in enumerate(sdo):
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sdo_sr = Signal(2*t_read - 2)
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sdo_sr0 = Signal(t_read - 1)
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sdo_sr1 = Signal(t_read - 1)
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sdo_ddr = Signal(2)
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self.specials += io.DDRInput(sdo, sdo_ddr[1], sdo_ddr[0],
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self.cd_ret.clk)
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self.sync.ret += [
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If(self.reading & sck_en_ret,
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sdo_sr.eq(Cat(sdo_ddr, sdo_sr))
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sdo_sr0.eq(Cat(sdo_ddr[0], sdo_sr0)),
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sdo_sr1.eq(Cat(sdo_ddr[1], sdo_sr1))
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)
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]
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self.comb += [
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Cat(reversed([self.data[i*k + j] for j in range(k)])).eq(
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Cat(sdo_ddr, sdo_sr))
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Cat(sdo_ddr, zip(sdo_sr0, sdo_sr1)))
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]
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