forked from M-Labs/artiq
coredevice/spi: clean up api
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@ -1,6 +1,6 @@
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from artiq.language.core import *
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from artiq.language.types import *
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from artiq.coredevice.rt2wb import *
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from artiq.language.units import MHz
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from artiq.coredevice.rt2wb import rt2wb_write, rt2wb_read_sync
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SPI_DATA_ADDR, SPI_XFER_ADDR, SPI_CONFIG_ADDR = range(3)
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@ -26,56 +26,63 @@ class SPIMaster:
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"""
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def __init__(self, dmgr, ref_period, channel):
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self.core = dmgr.get("core")
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self.ref_period = ref_period
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self.ref_period_mu = seconds_to_mu(ref_period, self.core)
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self.channel = channel
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self.write_div = 0
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self.read_div = 0
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# a full transfer takes prep_mu + xfer_mu
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self.prep_mu = 0
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# chained transfers can happen every xfer_mu
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self.xfer_mu = 0
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# The second transfer of a chain be written ref_period_mu
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# after the first. Read data is available every xfer_mu starting
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# a bit before prep_mu + xfer_mu.
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@portable
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def predict_xfer_mu(self, write_length, read_length):
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# this is only the intrinsic bit cycle duration
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return int(self.ref_period_mu*(
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write_length*self.write_div +
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read_length*self.read_div))
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@portable
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def predict_prep_mu(self, write_div):
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return int(self.ref_period_mu*(
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2 + # intermediate transfers
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# one write_div for the wait+idle cycle
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self.write_div))
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self.write_period_mu = 0
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self.read_period_mu = 0
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self.xfer_period_mu = 0
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# A full transfer takes write_period_mu + xfer_period_mu.
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# Chained transfers can happen every xfer_period_mu.
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# The second transfer of a chain can be written 2*ref_period_mu
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# after the first. Read data is available every xfer_period_mu starting
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# a bit after xfer_period_mu (depending on clk_phase).
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# To chain transfers together, new data must be written before
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# pending transfer's read data becomes available.
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@kernel
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def set_config(self, flags=0, write_div=6, read_div=6):
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self.write_div = write_div
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self.read_div = read_div
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self.prep_mu = self.predict_prep_mu(write_div)
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def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
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write_div = round(1/(write_freq*self.ref_period))
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read_div = round(1/(read_freq*self.ref_period))
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self.set_config_mu(flags, write_div, read_div)
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@kernel
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def set_config_mu(self, flags=0, write_div=6, read_div=6):
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rt2wb_write(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
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((write_div - 2) << 8) | ((read_div - 2) << 20))
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delay_mu(self.ref_period_mu)
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((write_div - 2) << 16) | ((read_div - 2) << 24))
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self.write_period_mu = int(write_div*self.ref_period_mu)
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self.read_period_mu = int(read_div*self.ref_period_mu)
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delay_mu(2*self.ref_period_mu)
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@portable
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def get_xfer_period_mu(self, write_length, read_length):
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return int(write_length*self.write_period_mu +
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read_length*self.read_period_mu)
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@kernel
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def set_xfer(self, chip_select=0, write_length=0, read_length=0):
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self.xfer_mu = self.predict_xfer_mu(write_length, read_length)
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rt2wb_write(now_mu(), self.channel, SPI_XFER_ADDR,
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chip_select | (write_length << 16) | (read_length << 24))
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delay_mu(self.ref_period_mu)
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self.xfer_period_mu = self.get_xfer_period_mu(
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write_length, read_length)
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delay_mu(int(2*self.ref_period_mu))
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@kernel
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def write(self, data):
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rt2wb_write(now_mu(), self.channel, SPI_DATA_ADDR, data)
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delay_mu(int(self.prep_mu + self.xfer_mu))
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delay_mu(int(self.write_period_mu + self.xfer_period_mu))
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@kernel
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def read_async(self):
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rt2wb_write(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
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delay_mu(int(2*self.ref_period_mu))
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@kernel
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def read_sync(self):
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r = rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR |
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SPI_RT2WB_READ, int(self.ref_period_mu))
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delay_mu(self.ref_period_mu)
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return r
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return rt2wb_read_sync(now_mu(), self.channel, SPI_DATA_ADDR |
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SPI_RT2WB_READ, int(2*self.ref_period_mu))
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@kernel
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def get_config_sync(self):
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return rt2wb_read_sync(now_mu(), self.channel, SPI_CONFIG_ADDR |
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SPI_RT2WB_READ, int(2*self.ref_period_mu))
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