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gateware.spi: ack only in cycles

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This commit is contained in:
Robert Jördens 2016-02-29 17:29:37 +01:00
parent a0083f4501
commit dd570720ac
1 changed files with 1 additions and 1 deletions
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artiq/gateware/spi.py
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@ -310,7 +310,7 @@ class SPIMaster(Module):
spi.div_read.eq(config.div_read),
]
self.sync += [
bus.ack.eq(~bus.we | ~pending | spi.done),
bus.ack.eq(bus.cyc & bus.stb & (~bus.we | ~pending | spi.done)),
If(wb_we,
Array([data_write, xfer.raw_bits(), config.raw_bits()
])[bus.adr].eq(bus.dat_w)