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spi: have write() delay by transfer duration

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This commit is contained in:
Robert Jördens 2016-03-03 21:57:27 +01:00
parent 423ca03f3b
commit dc6d116824
1 changed files with 3 additions and 3 deletions
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6
artiq/coredevice/spi.py
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@ -198,11 +198,11 @@ class SPIMaster:
the previous transfer's read data is available in the
``data`` register.
This method advances the timeline by the duration of the
RTIO-to-Wishbone bus transaction (three RTIO clock cycles).
This method advances the timeline by the duration of the SPI transfer.
If a transfer is to be chained, the timeline needs to be rewound.
"""
rtio_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
delay_mu(3*self.ref_period_mu)
delay_mu(self.xfer_period_mu + self.write_period_mu)
@kernel
def read_async(self):