From dc6d1168241a6953035a7939d11b4c1c05db9b7e Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 3 Mar 2016 21:57:27 +0100 Subject: [PATCH] spi: have write() delay by transfer duration --- artiq/coredevice/spi.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py index 264481e21..159bd4da4 100644 --- a/artiq/coredevice/spi.py +++ b/artiq/coredevice/spi.py @@ -198,11 +198,11 @@ class SPIMaster: the previous transfer's read data is available in the ``data`` register. - This method advances the timeline by the duration of the - RTIO-to-Wishbone bus transaction (three RTIO clock cycles). + This method advances the timeline by the duration of the SPI transfer. + If a transfer is to be chained, the timeline needs to be rewound. """ rtio_output(now_mu(), self.channel, SPI_DATA_ADDR, data) - delay_mu(3*self.ref_period_mu) + delay_mu(self.xfer_period_mu + self.write_period_mu) @kernel def read_async(self):