forked from M-Labs/artiq
rtio/sed: add minimum buffer space reporting
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63e39dec94
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@ -27,6 +27,9 @@ layout = [
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# o_status bits:
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# <0:wait> <1:underflow> <2:sequence_error>
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("o_status", 3, DIR_S_TO_M),
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# targets may optionally report a pessimistic estimate of the number
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# of outputs events that can be written without waiting.
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("o_buffer_space", 16, DIR_S_TO_M),
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("i_data", 32, DIR_S_TO_M),
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("i_timestamp", 64, DIR_S_TO_M),
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@ -13,7 +13,7 @@ __all__ = ["SED"]
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class SED(Module):
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def __init__(self, channels, glbl_fine_ts_width, mode,
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lane_count=8, fifo_depth=128, enable_spread=True,
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quash_channels=[], interface=None):
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quash_channels=[], interface=None, report_min_space=False):
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if mode == "sync":
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lane_dist_cdr = lambda x: x
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fifos_cdr = lambda x: x
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@ -37,7 +37,7 @@ class SED(Module):
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interface=interface))
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self.submodules.fifos = fifos_cdr(
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FIFOs(lane_count, fifo_depth,
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layouts.fifo_payload(channels), mode))
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layouts.fifo_payload(channels), mode, report_min_space))
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self.submodules.gates = gates_cdr(
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Gates(lane_count, seqn_width,
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layouts.fifo_payload(channels),
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@ -52,6 +52,9 @@ class SED(Module):
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for o, i in zip(self.gates.output, self.output_driver.input):
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self.comb += i.eq(o)
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if report_min_space:
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self.comb += self.cri.o_buffer_space.eq(self.fifos.min_space)
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@property
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def cri(self):
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return self.lane_dist.cri
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@ -1,3 +1,6 @@
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from operator import or_
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from functools import reduce
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from migen import *
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from migen.genlib.fifo import *
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@ -8,13 +11,18 @@ __all__ = ["FIFOs"]
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class FIFOs(Module):
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def __init__(self, lane_count, fifo_depth, layout_payload, mode):
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def __init__(self, lane_count, fifo_depth, layout_payload, mode, report_min_space=False):
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seqn_width = layouts.seqn_width(lane_count, fifo_depth)
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self.input = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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self.output = [Record(layouts.fifo_egress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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if report_min_space:
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self.min_space = Signal(max=fifo_depth+1)
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# # #
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if mode == "sync":
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fifo_cls = SyncFIFOBuffered
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elif mode == "async":
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@ -22,9 +30,11 @@ class FIFOs(Module):
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else:
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raise ValueError
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fifos = []
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for input, output in zip(self.input, self.output):
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fifo = fifo_cls(layout_len(layout_payload), fifo_depth)
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self.submodules += fifo
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fifos.append(fifo)
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self.comb += [
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fifo.din.eq(input.payload.raw_bits()),
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@ -35,3 +45,40 @@ class FIFOs(Module):
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output.readable.eq(fifo.readable),
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fifo.re.eq(output.re)
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]
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if report_min_space:
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if mode != "sync":
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raise NotImplementedError
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def compute_max(elts):
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l = len(elts)
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if l == 1:
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return elts[0], 0
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else:
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maximum1, latency1 = compute_max(elts[:l//2])
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maximum2, latency2 = compute_max(elts[l//2:])
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maximum = Signal(max(len(maximum1), len(maximum2)))
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self.sync += [
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If(maximum1 > maximum2,
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maximum.eq(maximum1)
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).Else(
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maximum.eq(maximum2)
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)
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]
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latency = max(latency1, latency2) + 1
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return maximum, latency
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max_level, latency = compute_max([fifo.level for fifo in fifos])
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max_level_valid = Signal()
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max_level_valid_counter = Signal(max=latency)
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self.sync += [
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If(reduce(or_, [fifo.we for fifo in fifos]),
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max_level_valid.eq(0),
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max_level_valid_counter.eq(latency - 1)
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).Elif(max_level_valid_counter == 0,
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max_level_valid.eq(1)
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).Else(
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max_level_valid_counter.eq(max_level_valid_counter - 1)
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)
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]
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self.comb += If(max_level_valid, self.min_space.eq(fifo_depth - max_level))
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