forked from M-Labs/artiq
sayma: print RTM gateware version
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d572c0c34d
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d7387611c0
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@ -1,5 +1,19 @@
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use core::{cmp, str};
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use board::csr;
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fn read_rtm_ident(buf: &mut [u8]) -> &str {
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unsafe {
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csr::rtm_identifier::address_write(0);
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let len = csr::rtm_identifier::data_read();
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let len = cmp::min(len, buf.len() as u8);
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for i in 0..len {
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csr::rtm_identifier::address_write(1 + i);
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buf[i as usize] = csr::rtm_identifier::data_read();
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}
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str::from_utf8_unchecked(&buf[..len as usize])
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}
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}
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unsafe fn debug_print(rtm: bool) {
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debug!("AMC serwb settings:");
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debug!(" delay_min_found: {}", csr::serwb_phy_amc::control_delay_min_found_read());
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@ -50,4 +64,6 @@ pub fn wait_init() {
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unsafe {
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debug_print(true);
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}
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info!("RTM gateware version {}", read_rtm_ident(&mut [0; 64]));
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}
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@ -9,12 +9,14 @@ from migen.build.platforms.sinara import sayma_rtm
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from misoc.interconnect import wishbone, stream
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from misoc.interconnect.csr import *
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from misoc.cores import identifier
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from misoc.cores import spi
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from misoc.cores import gpio
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from misoc.integration.wb_slaves import WishboneSlaveManager
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from misoc.integration.cpu_interface import get_csr_csv
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from artiq.gateware import serwb
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from artiq import __version__ as artiq_version
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class CRG(Module):
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@ -85,6 +87,8 @@ class SaymaRTM(Module):
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self.submodules.rtm_magic = RTMMagic()
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csr_devices.append("rtm_magic")
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self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
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csr_devices.append("rtm_identifier")
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# clock mux: 100MHz ext SMA clock to HMC830 input
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self.submodules.clock_mux = gpio.GPIOOut(Cat(
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