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sayma: print RTM gateware version

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This commit is contained in:
Sebastien Bourdeauducq 2018-02-15 19:31:58 +08:00
parent d572c0c34d
commit d7387611c0
2 changed files with 20 additions and 0 deletions
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16
artiq/firmware/libboard_artiq/serwb.rs
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@ -1,5 +1,19 @@
use core::{cmp, str};
use board::csr;
fn read_rtm_ident(buf: &mut [u8]) -> &str {
unsafe {
csr::rtm_identifier::address_write(0);
let len = csr::rtm_identifier::data_read();
let len = cmp::min(len, buf.len() as u8);
for i in 0..len {
csr::rtm_identifier::address_write(1 + i);
buf[i as usize] = csr::rtm_identifier::data_read();
}
str::from_utf8_unchecked(&buf[..len as usize])
}
}
unsafe fn debug_print(rtm: bool) {
debug!("AMC serwb settings:");
debug!(" delay_min_found: {}", csr::serwb_phy_amc::control_delay_min_found_read());
@ -50,4 +64,6 @@ pub fn wait_init() {
unsafe {
debug_print(true);
}
info!("RTM gateware version {}", read_rtm_ident(&mut [0; 64]));
}

4
artiq/gateware/targets/sayma_rtm.py
View File

@ -9,12 +9,14 @@ from migen.build.platforms.sinara import sayma_rtm
from misoc.interconnect import wishbone, stream
from misoc.interconnect.csr import *
from misoc.cores import identifier
from misoc.cores import spi
from misoc.cores import gpio
from misoc.integration.wb_slaves import WishboneSlaveManager
from misoc.integration.cpu_interface import get_csr_csv
from artiq.gateware import serwb
from artiq import __version__ as artiq_version
class CRG(Module):
@ -85,6 +87,8 @@ class SaymaRTM(Module):
self.submodules.rtm_magic = RTMMagic()
csr_devices.append("rtm_magic")
self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
csr_devices.append("rtm_identifier")
# clock mux: 100MHz ext SMA clock to HMC830 input
self.submodules.clock_mux = gpio.GPIOOut(Cat(