From d7387611c0b7c9439ae03e059f4ac0ca188d852e Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Thu, 15 Feb 2018 19:31:58 +0800
Subject: [PATCH] sayma: print RTM gateware version

---
 artiq/firmware/libboard_artiq/serwb.rs | 16 ++++++++++++++++
 artiq/gateware/targets/sayma_rtm.py    |  4 ++++
 2 files changed, 20 insertions(+)

diff --git a/artiq/firmware/libboard_artiq/serwb.rs b/artiq/firmware/libboard_artiq/serwb.rs
index 39dff6fd4..fea567172 100644
--- a/artiq/firmware/libboard_artiq/serwb.rs
+++ b/artiq/firmware/libboard_artiq/serwb.rs
@@ -1,5 +1,19 @@
+use core::{cmp, str};
 use board::csr;
 
+fn read_rtm_ident(buf: &mut [u8]) -> &str {
+    unsafe {
+        csr::rtm_identifier::address_write(0);
+        let len = csr::rtm_identifier::data_read();
+        let len = cmp::min(len, buf.len() as u8);
+        for i in 0..len {
+            csr::rtm_identifier::address_write(1 + i);
+            buf[i as usize] = csr::rtm_identifier::data_read();
+        }
+        str::from_utf8_unchecked(&buf[..len as usize])
+    }
+}
+
 unsafe fn debug_print(rtm: bool) {
     debug!("AMC serwb settings:");
     debug!("  delay_min_found: {}", csr::serwb_phy_amc::control_delay_min_found_read());
@@ -50,4 +64,6 @@ pub fn wait_init() {
     unsafe {
         debug_print(true);
     }
+
+    info!("RTM gateware version {}", read_rtm_ident(&mut [0; 64]));
 }
diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py
index c6575c2d1..9a77a4694 100755
--- a/artiq/gateware/targets/sayma_rtm.py
+++ b/artiq/gateware/targets/sayma_rtm.py
@@ -9,12 +9,14 @@ from migen.build.platforms.sinara import sayma_rtm
 
 from misoc.interconnect import wishbone, stream
 from misoc.interconnect.csr import *
+from misoc.cores import identifier
 from misoc.cores import spi
 from misoc.cores import gpio
 from misoc.integration.wb_slaves import WishboneSlaveManager
 from misoc.integration.cpu_interface import get_csr_csv
 
 from artiq.gateware import serwb
+from artiq import __version__ as artiq_version
 
 
 class CRG(Module):
@@ -85,6 +87,8 @@ class SaymaRTM(Module):
 
         self.submodules.rtm_magic = RTMMagic()
         csr_devices.append("rtm_magic")
+        self.submodules.rtm_identifier = identifier.Identifier(artiq_version)
+        csr_devices.append("rtm_identifier")
 
         # clock mux: 100MHz ext SMA clock to HMC830 input
         self.submodules.clock_mux = gpio.GPIOOut(Cat(