srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

satman: tune Sayma SYSREF phases

This commit is contained in:
Sebastien Bourdeauducq 2018-06-27 18:09:35 +08:00
parent 46c044099c
commit d49716dfac
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/firmware/satman/main.rs
View File

@ -250,9 +250,9 @@ fn drtio_link_rx_up() -> bool {
const SIPHASER_PHASE: u16 = 32;
#[cfg(has_ad9154)]
const SYSREF_PHASE_FPGA: u16 = 32;
const SYSREF_PHASE_FPGA: u16 = 53;
#[cfg(has_ad9154)]
const SYSREF_PHASE_DAC: u16 = 61;
const SYSREF_PHASE_DAC: u16 = 64;
#[no_mangle]
pub extern fn main() -> i32 {