forked from M-Labs/artiq
hmc7043,satman: verify alignment of SYSREF slips
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@ -769,7 +769,7 @@ pub fn init(sysref_phase_fpga: u16, sysref_phase_dac: u16) {
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// the HMC7043 input clock (which defines slip resolution)
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// is 2x the DAC clock, so there are two possible phases from
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// the divider states. This deterministically selects one.
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hmc7043::sysref_rtio_align(sysref_phase_fpga);
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hmc7043::sysref_rtio_align(sysref_phase_fpga, 1);
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for dacno in 0..csr::AD9154.len() {
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// We assume DCLK and SYSREF traces are matched on the PCB
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@ -158,13 +158,13 @@ pub mod hmc7043 {
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use board_misoc::{csr, clock};
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// All frequencies assume 1.2GHz HMC830 output
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const DAC_CLK_DIV: u32 = 2; // 600MHz
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const FPGA_CLK_DIV: u32 = 8; // 150MHz
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const SYSREF_DIV: u32 = 128; // 9.375MHz
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const HMC_SYSREF_DIV: u32 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)
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pub const DAC_CLK_DIV: u16 = 2; // 600MHz
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pub const FPGA_CLK_DIV: u16 = 8; // 150MHz
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pub const SYSREF_DIV: u16 = 128; // 9.375MHz
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pub const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)
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// enabled, divider, output config
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const OUTPUT_CONFIG: [(bool, u32, u8); 14] = [
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const OUTPUT_CONFIG: [(bool, u16, u8); 14] = [
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(true, DAC_CLK_DIV, 0x08), // 0: DAC2_CLK
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(true, SYSREF_DIV, 0x08), // 1: DAC2_SYSREF
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(true, DAC_CLK_DIV, 0x08), // 2: DAC1_CLK
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@ -355,7 +355,7 @@ pub mod hmc7043 {
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unsafe { csr::sysref_sampler::sample_result_read() == 1 }
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}
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pub fn sysref_rtio_align(phase_offset: u16) {
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pub fn sysref_rtio_align(phase_offset: u16, expected_align: u16) {
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info!("aligning SYSREF with RTIO...");
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let mut slips0 = 0;
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@ -380,7 +380,10 @@ pub mod hmc7043 {
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break;
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}
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}
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info!(" ...done ({}/{} slips), verifying timing margin", slips0, slips1);
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info!(" ...done ({}/{} slips)", slips0, slips1);
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if (slips0 + slips1) % expected_align != 0 {
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error!(" unexpected slip alignment");
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}
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let mut margin_minus = None;
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for d in 0..phase_offset {
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@ -298,7 +298,10 @@ pub extern fn main() -> i32 {
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#[cfg(has_hmc830_7043)]
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{
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if drtio_tsc_loaded() {
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hmc830_7043::hmc7043::sysref_rtio_align(SYSREF_PHASE_FPGA);
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// Expected alignment: 1 RTIO clock period
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hmc830_7043::hmc7043::sysref_rtio_align(
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SYSREF_PHASE_FPGA,
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hmc830_7043::hmc7043::FPGA_CLK_DIV);
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}
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}
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}
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