forked from M-Labs/artiq
ad9910: fix pll timeout loop
Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -166,17 +166,19 @@ class AD9910:
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self.cpld.io_update.pulse(1*us)
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if blind:
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delay(100*ms)
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return
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# Wait for PLL lock, up to 100 ms
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for i in range(100):
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sta = self.cpld.sta_read()
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lock = urukul_sta_pll_lock(sta)
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delay(1*ms)
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if lock & (1 << self.chip_select - 4):
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return
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raise ValueError("PLL lock timeout")
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else:
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# Wait for PLL lock, up to 100 ms
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for i in range(100):
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sta = self.cpld.sta_read()
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lock = urukul_sta_pll_lock(sta)
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delay(1*ms)
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if lock & (1 << self.chip_select - 4):
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break
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if i >= 100 - 1:
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raise ValueError("PLL lock timeout")
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if self.sync_delay_seed >= 0:
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self.tune_sync_delay(self.sync_delay_seed)
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delay(1*ms)
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@kernel
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def power_down(self, bits=0b1111):
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