From d3ad2b7633acc94773a65fddcbd7fc52be40057d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 2 Nov 2018 12:22:42 +0000 Subject: [PATCH] ad9910: fix pll timeout loop MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Robert Jördens --- artiq/coredevice/ad9910.py | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index 8091614cb..321d0ee1e 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -166,17 +166,19 @@ class AD9910: self.cpld.io_update.pulse(1*us) if blind: delay(100*ms) - return - # Wait for PLL lock, up to 100 ms - for i in range(100): - sta = self.cpld.sta_read() - lock = urukul_sta_pll_lock(sta) - delay(1*ms) - if lock & (1 << self.chip_select - 4): - return - raise ValueError("PLL lock timeout") + else: + # Wait for PLL lock, up to 100 ms + for i in range(100): + sta = self.cpld.sta_read() + lock = urukul_sta_pll_lock(sta) + delay(1*ms) + if lock & (1 << self.chip_select - 4): + break + if i >= 100 - 1: + raise ValueError("PLL lock timeout") if self.sync_delay_seed >= 0: self.tune_sync_delay(self.sync_delay_seed) + delay(1*ms) @kernel def power_down(self, bits=0b1111):