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ad9910: ensure sync is driven when required 

close #1194

Signed-off-by: Robert Jördens <rj@quartiq.de>
This commit is contained in:
Robert Jördens 2018-11-16 13:17:43 +00:00
parent de9d21ffc8
commit d1eee7c0ea
1 changed files with 4 additions and 0 deletions
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4
artiq/coredevice/ad9910.py
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@ -101,6 +101,8 @@ class AD9910:
self.pll_vco = pll_vco self.pll_vco = pll_vco
assert 0 <= pll_cp <= 7 assert 0 <= pll_cp <= 7
self.pll_cp = pll_cp self.pll_cp = pll_cp
if sync_delay_seed >= 0 and not self.cpld.sync_div:
raise ValueError("parent cpld does not drive SYNC")
self.sync_delay_seed = sync_delay_seed self.sync_delay_seed = sync_delay_seed
self.io_update_delay = io_update_delay self.io_update_delay = io_update_delay
self.phase_mode = PHASE_MODE_CONTINUOUS self.phase_mode = PHASE_MODE_CONTINUOUS
@ -430,6 +432,8 @@ class AD9910:
Defaults to 15 (half range). Defaults to 15 (half range).
:return: Tuple of optimal delay and window size. :return: Tuple of optimal delay and window size.
""" """
if not self.cpld.sync_div:
raise ValueError("parent cpld does not drive SYNC")
search_span = 31 search_span = 31
# FIXME https://github.com/sinara-hw/Urukul/issues/16 # FIXME https://github.com/sinara-hw/Urukul/issues/16
# should both be 2-4 once kasli sync_in jitter is identified # should both be 2-4 once kasli sync_in jitter is identified