From d1eee7c0ea4d8e19404dbfa5dacd1ee4272b28b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Robert=20J=C3=B6rdens?= Date: Fri, 16 Nov 2018 13:17:43 +0000 Subject: [PATCH] ad9910: ensure sync is driven when required MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit close #1194 Signed-off-by: Robert Jördens --- artiq/coredevice/ad9910.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index ae5842808..5d171ac55 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -101,6 +101,8 @@ class AD9910: self.pll_vco = pll_vco assert 0 <= pll_cp <= 7 self.pll_cp = pll_cp + if sync_delay_seed >= 0 and not self.cpld.sync_div: + raise ValueError("parent cpld does not drive SYNC") self.sync_delay_seed = sync_delay_seed self.io_update_delay = io_update_delay self.phase_mode = PHASE_MODE_CONTINUOUS @@ -430,6 +432,8 @@ class AD9910: Defaults to 15 (half range). :return: Tuple of optimal delay and window size. """ + if not self.cpld.sync_div: + raise ValueError("parent cpld does not drive SYNC") search_span = 31 # FIXME https://github.com/sinara-hw/Urukul/issues/16 # should both be 2-4 once kasli sync_in jitter is identified