forked from M-Labs/artiq
ad9910: ensure sync is driven when required
close #1194 Signed-off-by: Robert Jördens <rj@quartiq.de>
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@ -101,6 +101,8 @@ class AD9910:
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self.pll_vco = pll_vco
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assert 0 <= pll_cp <= 7
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self.pll_cp = pll_cp
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if sync_delay_seed >= 0 and not self.cpld.sync_div:
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raise ValueError("parent cpld does not drive SYNC")
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self.sync_delay_seed = sync_delay_seed
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self.io_update_delay = io_update_delay
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self.phase_mode = PHASE_MODE_CONTINUOUS
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@ -430,6 +432,8 @@ class AD9910:
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Defaults to 15 (half range).
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:return: Tuple of optimal delay and window size.
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"""
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if not self.cpld.sync_div:
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raise ValueError("parent cpld does not drive SYNC")
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search_span = 31
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# FIXME https://github.com/sinara-hw/Urukul/issues/16
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# should both be 2-4 once kasli sync_in jitter is identified
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