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rtio/phy/ttl_simple: reset sensitivity with RTIO logic

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Sebastien Bourdeauducq 2015-05-02 16:17:31 +08:00
parent d8fdac6f86
commit cb65b1e322
1 changed files with 5 additions and 6 deletions
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11
artiq/gateware/rtio/phy/ttl_simple.py
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@ -26,12 +26,11 @@ class Inout(Module):
sensitivity = Signal(2) sensitivity = Signal(2)
self.sync.rio_phy += If(self.rtlink.o.stb, self.sync.rio_phy += If(self.rtlink.o.stb,
Case(self.rtlink.o.address, { If(self.rtlink.o.address == 0, ts.o.eq(self.rtlink.o.data[0])),
0: ts.o.eq(self.rtlink.o.data[0]), If(self.rtlink.o.address == 1, ts.oe.eq(self.rtlink.o.data[0])),
1: ts.oe.eq(self.rtlink.o.data[0]), )
2: sensitivity.eq(self.rtlink.o.data) self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2),
}).makedefault() sensitivity.eq(self.rtlink.o.data))
)
i = Signal() i = Signal()
i_d = Signal() i_d = Signal()