From cb65b1e3228ed5657080e619801cd90f9de7203a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 2 May 2015 16:17:31 +0800 Subject: [PATCH] rtio/phy/ttl_simple: reset sensitivity with RTIO logic --- artiq/gateware/rtio/phy/ttl_simple.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/rtio/phy/ttl_simple.py b/artiq/gateware/rtio/phy/ttl_simple.py index 8a27fcb9a..ce6f953cb 100644 --- a/artiq/gateware/rtio/phy/ttl_simple.py +++ b/artiq/gateware/rtio/phy/ttl_simple.py @@ -26,12 +26,11 @@ class Inout(Module): sensitivity = Signal(2) self.sync.rio_phy += If(self.rtlink.o.stb, - Case(self.rtlink.o.address, { - 0: ts.o.eq(self.rtlink.o.data[0]), - 1: ts.oe.eq(self.rtlink.o.data[0]), - 2: sensitivity.eq(self.rtlink.o.data) - }).makedefault() - ) + If(self.rtlink.o.address == 0, ts.o.eq(self.rtlink.o.data[0])), + If(self.rtlink.o.address == 1, ts.oe.eq(self.rtlink.o.data[0])), + ) + self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2), + sensitivity.eq(self.rtlink.o.data)) i = Signal() i_d = Signal()