kasli: add Tsinghua variant

artiq/examples/kasli_basic/device_db_tsinghua.py

@@ -0,0 +1,187 @@
+core_addr = "kasli-1.lab.m-labs.hk"
+
+device_db = {
+    "core": {
+        "type": "local",
+        "module": "artiq.coredevice.core",
+        "class": "Core",
+        "arguments": {"host": core_addr, "ref_period": 1e-9}
+    },
+    "core_log": {
+        "type": "controller",
+        "host": "::1",
+        "port": 1068,
+        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
+    },
+    "core_cache": {
+        "type": "local",
+        "module": "artiq.coredevice.cache",
+        "class": "CoreCache"
+    },
+    "core_dma": {
+        "type": "local",
+        "module": "artiq.coredevice.dma",
+        "class": "CoreDMA"
+    },
+
+    "i2c_switch0": {
+        "type": "local",
+        "module": "artiq.coredevice.i2c",
+        "class": "PCA9548",
+        "arguments": {"address": 0xe0}
+    },
+    "i2c_switch1": {
+        "type": "local",
+        "module": "artiq.coredevice.i2c",
+        "class": "PCA9548",
+        "arguments": {"address": 0xe2}
+    },
+}
+
+
+for i in range(8):
+    device_db["ttl" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut" if i < 4 else "TTLOut",
+        "arguments": {"channel": i},
+    }
+
+
+device_db.update(
+    spi_urukul0={
+        "type": "local",
+        "module": "artiq.coredevice.spi2",
+        "class": "SPIMaster",
+        "arguments": {"channel": 8}
+    },
+    ttl_urukul0_io_update={
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 9}
+    },
+    ttl_urukul0_sw0={
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 10}
+    },
+    ttl_urukul0_sw1={
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 11}
+    },
+    ttl_urukul0_sw2={
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 12}
+    },
+    ttl_urukul0_sw3={
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 13}
+    },
+    urukul0_cpld={
+        "type": "local",
+        "module": "artiq.coredevice.urukul",
+        "class": "CPLD",
+        "arguments": {
+            "spi_device": "spi_urukul0",
+            "io_update_device": "ttl_urukul0_io_update",
+            "refclk": 125e6,
+            "clk_sel": 0
+        }
+    }
+)
+
+for i in range(4):
+    device_db["urukul0_ch" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.ad9910",
+        "class": "AD9910",
+        "arguments": {
+            "pll_n": 32,
+            "chip_select": 4 + i,
+            "cpld_device": "urukul0_cpld",
+            "sw_device": "ttl_urukul0_sw" + str(i)
+        }
+    }
+
+
+device_db["spi_sampler0_adc"] = {
+    "type": "local",
+    "module": "artiq.coredevice.spi2",
+    "class": "SPIMaster",
+    "arguments": {"channel": 14}
+}
+device_db["spi_sampler0_pgia"] = {
+    "type": "local",
+    "module": "artiq.coredevice.spi2",
+    "class": "SPIMaster",
+    "arguments": {"channel": 15}
+}
+device_db["spi_sampler0_cnv"] = {
+    "type": "local",
+    "module": "artiq.coredevice.ttl",
+    "class": "TTLOut",
+    "arguments": {"channel": 16},
+}
+device_db["sampler0"] = {
+    "type": "local",
+    "module": "artiq.coredevice.sampler",
+    "class": "Sampler",
+    "arguments": {
+        "spi_adc_device": "spi_sampler0_adc",
+        "spi_pgia_device": "spi_sampler0_pgia",
+        "cnv_device": "spi_sampler0_cnv"
+    }
+}
+
+
+device_db["spi_zotino0"] = {
+    "type": "local",
+    "module": "artiq.coredevice.spi2",
+    "class": "SPIMaster",
+    "arguments": {"channel": 17}
+}
+device_db["ttl_zotino0_ldac"] = {
+    "type": "local",
+    "module": "artiq.coredevice.ttl",
+    "class": "TTLOut",
+    "arguments": {"channel": 18}
+}
+device_db["ttl_zotino0_clr"] = {
+    "type": "local",
+    "module": "artiq.coredevice.ttl",
+    "class": "TTLOut",
+    "arguments": {"channel": 19}
+}
+device_db["zotino0"] = {
+    "type": "local",
+    "module": "artiq.coredevice.zotino",
+    "class": "Zotino",
+    "arguments": {
+        "spi_device": "spi_zotino0",
+        "ldac_device": "ttl_zotino0_ldac",
+        "clr_device": "ttl_zotino0_clr"
+    }
+}
+
+device_db.update(
+    led0={
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 22}
+    },
+    led1={
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 23}
+    },
+)

artiq/gateware/targets/kasli.py

@@ -341,6 +341,42 @@ class USTC(_StandaloneBase):
         self.add_csr_group("grabber", self.grabber_csr_group)
 
 
+class Tsinghua(_StandaloneBase):
+    def __init__(self, hw_rev=None, **kwargs):
+        if hw_rev is None:
+            hw_rev = "v1.1"
+        _StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
+
+        self.config["SI5324_AS_SYNTHESIZER"] = None
+        self.config["RTIO_FREQUENCY"] = "125.0"
+        if hw_rev == "v1.0":
+            # EEM clock fan-out from Si5324, not MMCX
+            self.comb += self.platform.request("clk_sel").eq(1)
+
+        self.rtio_channels = []
+        self.grabber_csr_group = []
+        eem.DIO.add_std(self, 4,
+            ttl_serdes_7series.InOut_8X, ttl_serdes_7series.Output_8X)
+        eem.Urukul.add_std(self, 3, 2, ttl_serdes_7series.Output_8X)
+        eem.Sampler.add_std(self, 6, 5, ttl_serdes_7series.Output_8X)
+        eem.Zotino.add_std(self, 7, ttl_serdes_7series.Output_8X)
+        eem.Grabber.add_std(self, 1, 0)
+
+        for i in (1, 2):
+            sfp_ctl = self.platform.request("sfp_ctl", i)
+            phy = ttl_simple.Output(sfp_ctl.led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        self.config["HAS_RTIO_LOG"] = None
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.add_rtio(self.rtio_channels)
+        self.config["HAS_GRABBER"] = None
+        self.add_csr_group("grabber", self.grabber_csr_group)
+
+
 class PTB(_StandaloneBase):
     """PTB Kasli variant
 
@@ -808,7 +844,7 @@ def main():
     soc_kasli_args(parser)
     parser.set_defaults(output_dir="artiq_kasli")
     variants = {cls.__name__.lower(): cls for cls in [
-        Opticlock, SUServo, SYSU, MITLL, USTC, PTB, HUB, LUH,
+        Opticlock, SUServo, SYSU, MITLL, USTC, Tsinghua, PTB, HUB, LUH,
         Tester, Master, Satellite]}
     parser.add_argument("-V", "--variant", default="opticlock",
                         help="variant: {} (default: %(default)s)".format(