forked from M-Labs/artiq
parent
e21b7965b9
commit
38971d130a
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@ -381,7 +381,8 @@ class SPIMaster2Handler(WishboneHandler):
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else:
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raise ValueError("bad address", address)
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# process untimed reads and insert them here
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while self._reads[0].rtio_counter < message.timestamp:
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while (self._reads and
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self._reads[0].rtio_counter < message.timestamp):
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read = self._reads.pop(0)
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logger.debug("SPI read @%d data=0x%08x",
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read.rtio_counter, read.data)
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