From c769bdab9b96ef1d2e163101628b28b6eb5eec73 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 30 May 2014 18:20:13 +0200 Subject: [PATCH] Introduce compiler and device modules --- {examples => artiq/compiler}/transform.py | 10 ++++---- artiq/{ => compiler}/unparse.py | 0 artiq/devices/core.py | 5 ++++ artiq/devices/core_dds.py | 25 +++++++++++++++++++ artiq/language/experiment.py | 7 ++++-- artiq/sim/devices.py | 4 ++-- examples/collapse_test.py | 9 ------- examples/compiler_test.py | 29 +++++++++++++++++++++++ 8 files changed, 70 insertions(+), 19 deletions(-) rename {examples => artiq/compiler}/transform.py (96%) rename artiq/{ => compiler}/unparse.py (100%) create mode 100644 artiq/devices/core.py create mode 100644 artiq/devices/core_dds.py delete mode 100644 examples/collapse_test.py create mode 100644 examples/compiler_test.py diff --git a/examples/transform.py b/artiq/compiler/transform.py similarity index 96% rename from examples/transform.py rename to artiq/compiler/transform.py index 8f0e89a85..75351e3ab 100644 --- a/examples/transform.py +++ b/artiq/compiler/transform.py @@ -1,6 +1,7 @@ import inspect, textwrap, ast, types -from artiq import units, unparse +from artiq.language import units +from artiq.compiler import unparse def find_kernel_body(node): while True: @@ -196,11 +197,8 @@ def collapse(stmts): stmts[offset+location:offset+location+1] = new_stmts offset += len(new_stmts) - 1 -if __name__ == "__main__": - import collapse_test - kernel = collapse_test.collapse_test - - node = ast.parse(textwrap.dedent(inspect.getsource(kernel))) +def transform(k_function, k_args, k_kwargs): + node = ast.parse(textwrap.dedent(inspect.getsource(k_function))) node = find_kernel_body(node) explicit_delays(node) diff --git a/artiq/unparse.py b/artiq/compiler/unparse.py similarity index 100% rename from artiq/unparse.py rename to artiq/compiler/unparse.py diff --git a/artiq/devices/core.py b/artiq/devices/core.py new file mode 100644 index 000000000..9916f8431 --- /dev/null +++ b/artiq/devices/core.py @@ -0,0 +1,5 @@ +from artiq.compiler.transform import transform + +class Core: + def run(self, k_function, *k_args, **k_kwargs): + transform(k_function, k_args, k_kwargs) diff --git a/artiq/devices/core_dds.py b/artiq/devices/core_dds.py new file mode 100644 index 000000000..27a7fd5cf --- /dev/null +++ b/artiq/devices/core_dds.py @@ -0,0 +1,25 @@ +from artiq.language.experiment import * +from artiq.language.units import * + +class DDS: + def __init__(self, core, reg_channel, rtio_channel, latency=0*ps, phase_mode="continuous"): + self.core = core + self.reg_channel = reg_channel + self.rtio_channel = rtio_channel + self.latency = latency + self.phase_mode = phase_mode + + self._previous_frequency = 0*MHz + + kernel_attr_ro = {"reg_channel", "rtio_channel", "latency", "phase_mode"} + kernel_attr = {"_previous_frequency"} + + @kernel + def pulse(self, frequency, duration): + if self._previous_frequency != frequency: + self.core.syscall("rtio_sync", self.rtio_channel) # wait until output is off + self.core.syscall("dds_program", self.reg_channel, frequency) + self._previous_frequency = frequency + self.core.syscall("rtio_set", now()-self.latency, self.rtio_channel, 1) + delay(duration) + self.core.syscall("rtio_set", now()-self.latency, self.rtio_channel, 0) diff --git a/artiq/language/experiment.py b/artiq/language/experiment.py index 019c474dd..76a51e1f1 100644 --- a/artiq/language/experiment.py +++ b/artiq/language/experiment.py @@ -1,6 +1,9 @@ import itertools class Experiment: + channels = "" + parameters = "" + def __init__(self, *args, **kwargs): channels = self.channels.split() parameters = self.parameters.split() @@ -24,9 +27,9 @@ class Experiment: def kernel(arg): if isinstance(arg, str): - def real_decorator(function): + def real_decorator(k_function): def run_on_core(exp, *k_args, **k_kwargs): - getattr(exp, arg).run(function, exp, *k_args, **k_kwargs) + getattr(exp, arg).run(k_function, exp, *k_args, **k_kwargs) return run_on_core return real_decorator else: diff --git a/artiq/sim/devices.py b/artiq/sim/devices.py index 4d0039445..2e28149ba 100644 --- a/artiq/sim/devices.py +++ b/artiq/sim/devices.py @@ -4,8 +4,8 @@ from artiq.language import units from artiq.sim import time class Core: - def run(self, function, *args, **kwargs): - return function(*args, **kwargs) + def run(self, k_function, *k_args, **k_kwargs): + return k_function(*k_args, **k_kwargs) class Input: def __init__(self, name, prng_seed=None, wait_max=20, count_max=100, wait_min=0, count_min=0): diff --git a/examples/collapse_test.py b/examples/collapse_test.py deleted file mode 100644 index 99012cd55..000000000 --- a/examples/collapse_test.py +++ /dev/null @@ -1,9 +0,0 @@ -def collapse_test(): - for i in range(3): - with parallel: - with sequential: - pulse("a", 100*MHz, 20*us) - pulse("b", 100*MHz, 10*us) - with sequential: - pulse("A", 100*MHz, 10*us) - pulse("B", 100*MHz, 10*us) diff --git a/examples/compiler_test.py b/examples/compiler_test.py new file mode 100644 index 000000000..a75565ec5 --- /dev/null +++ b/examples/compiler_test.py @@ -0,0 +1,29 @@ +from artiq.language.units import * +from artiq.language.experiment import * + +class CompilerTest(Experiment): + channels = "core a b A B" + + @kernel + def run(): + for i in range(3): + with parallel: + with sequential: + self.a.pulse(100*MHz, 20*us) + self.b.pulse(100*MHz, 10*us) + with sequential: + self.A.pulse(100*MHz, 10*us) + self.B.pulse(100*MHz, 10*us) + +if __name__ == "__main__": + from artiq.devices import core, core_dds + + coredev = core.Core() + exp = CompilerTest( + core=coredev, + a=core_dds.DDS(coredev, 0, 0), + b=core_dds.DDS(coredev, 1, 1), + A=core_dds.DDS(coredev, 2, 2), + B=core_dds.DDS(coredev, 3, 3) + ) + exp.run()