forked from M-Labs/artiq
firmware: support moninj without DDS. Closes #650
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455250b3f9
commit
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@ -18,6 +18,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
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match request {
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Request::Monitor => {
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#[cfg(has_dds)]
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let mut dds_ftws = [0u32; (csr::CONFIG_RTIO_DDS_COUNT as usize *
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csr::CONFIG_DDS_CHANNELS_PER_BUS as usize)];
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let mut reply = Reply::default();
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@ -43,22 +44,25 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> {
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}
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}
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reply.dds_rtio_first_channel = csr::CONFIG_RTIO_FIRST_DDS_CHANNEL as u16;
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reply.dds_channels_per_bus = csr::CONFIG_DDS_CHANNELS_PER_BUS as u16;
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#[cfg(has_dds)]
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{
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reply.dds_rtio_first_channel = csr::CONFIG_RTIO_FIRST_DDS_CHANNEL as u16;
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reply.dds_channels_per_bus = csr::CONFIG_DDS_CHANNELS_PER_BUS as u16;
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for j in 0..csr::CONFIG_RTIO_DDS_COUNT {
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unsafe {
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csr::rtio_moninj::mon_chan_sel_write(
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(csr::CONFIG_RTIO_FIRST_DDS_CHANNEL + j) as u8);
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for i in 0..csr::CONFIG_DDS_CHANNELS_PER_BUS {
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csr::rtio_moninj::mon_probe_sel_write(i as u8);
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csr::rtio_moninj::mon_value_update_write(1);
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dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
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csr::rtio_moninj::mon_value_read() as u32;
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for j in 0..csr::CONFIG_RTIO_DDS_COUNT {
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unsafe {
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csr::rtio_moninj::mon_chan_sel_write(
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(csr::CONFIG_RTIO_FIRST_DDS_CHANNEL + j) as u8);
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for i in 0..csr::CONFIG_DDS_CHANNELS_PER_BUS {
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csr::rtio_moninj::mon_probe_sel_write(i as u8);
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csr::rtio_moninj::mon_value_update_write(1);
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dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] =
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csr::rtio_moninj::mon_value_read() as u32;
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}
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}
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}
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reply.dds_ftws = &dds_ftws;
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}
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reply.dds_ftws = &dds_ftws;
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trace!("{} <- {:?}", addr, reply);
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buf.clear();
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@ -230,12 +230,6 @@ class Phaser(MiniSoC, AMPSoC):
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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# TODO: get rid of those bogus DDS defines
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# currently moninj in the runtime requires them
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self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels)
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self.config["RTIO_DDS_COUNT"] = 1
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self.config["DDS_CHANNELS_PER_BUS"] = 1
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self.submodules.rtio_crg = _PhaserCRG(
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platform, self.ad9154.jesd.cd_jesd.clk)
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self.csr_devices.append("rtio_crg")
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