From c08fc8aae94ca980cbd660f885fd9d7a0bd972f3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 4 Jan 2017 11:25:52 +0100 Subject: [PATCH] firmware: support moninj without DDS. Closes #650 --- artiq/firmware/runtime/moninj.rs | 28 ++++++++++++++++------------ artiq/gateware/targets/phaser.py | 6 ------ 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/artiq/firmware/runtime/moninj.rs b/artiq/firmware/runtime/moninj.rs index 4db0aca0f..16759cff9 100644 --- a/artiq/firmware/runtime/moninj.rs +++ b/artiq/firmware/runtime/moninj.rs @@ -18,6 +18,7 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> { match request { Request::Monitor => { + #[cfg(has_dds)] let mut dds_ftws = [0u32; (csr::CONFIG_RTIO_DDS_COUNT as usize * csr::CONFIG_DDS_CHANNELS_PER_BUS as usize)]; let mut reply = Reply::default(); @@ -43,22 +44,25 @@ fn worker(socket: &mut UdpSocket) -> io::Result<()> { } } - reply.dds_rtio_first_channel = csr::CONFIG_RTIO_FIRST_DDS_CHANNEL as u16; - reply.dds_channels_per_bus = csr::CONFIG_DDS_CHANNELS_PER_BUS as u16; + #[cfg(has_dds)] + { + reply.dds_rtio_first_channel = csr::CONFIG_RTIO_FIRST_DDS_CHANNEL as u16; + reply.dds_channels_per_bus = csr::CONFIG_DDS_CHANNELS_PER_BUS as u16; - for j in 0..csr::CONFIG_RTIO_DDS_COUNT { - unsafe { - csr::rtio_moninj::mon_chan_sel_write( - (csr::CONFIG_RTIO_FIRST_DDS_CHANNEL + j) as u8); - for i in 0..csr::CONFIG_DDS_CHANNELS_PER_BUS { - csr::rtio_moninj::mon_probe_sel_write(i as u8); - csr::rtio_moninj::mon_value_update_write(1); - dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] = - csr::rtio_moninj::mon_value_read() as u32; + for j in 0..csr::CONFIG_RTIO_DDS_COUNT { + unsafe { + csr::rtio_moninj::mon_chan_sel_write( + (csr::CONFIG_RTIO_FIRST_DDS_CHANNEL + j) as u8); + for i in 0..csr::CONFIG_DDS_CHANNELS_PER_BUS { + csr::rtio_moninj::mon_probe_sel_write(i as u8); + csr::rtio_moninj::mon_value_update_write(1); + dds_ftws[(csr::CONFIG_DDS_CHANNELS_PER_BUS * j + i) as usize] = + csr::rtio_moninj::mon_value_read() as u32; + } } } + reply.dds_ftws = &dds_ftws; } - reply.dds_ftws = &dds_ftws; trace!("{} <- {:?}", addr, reply); buf.clear(); diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index b5392f60a..83362ee72 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -230,12 +230,6 @@ class Phaser(MiniSoC, AMPSoC): self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) rtio_channels.append(rtio.LogChannel()) - # TODO: get rid of those bogus DDS defines - # currently moninj in the runtime requires them - self.config["RTIO_FIRST_DDS_CHANNEL"] = len(rtio_channels) - self.config["RTIO_DDS_COUNT"] = 1 - self.config["DDS_CHANNELS_PER_BUS"] = 1 - self.submodules.rtio_crg = _PhaserCRG( platform, self.ad9154.jesd.cd_jesd.clk) self.csr_devices.append("rtio_crg")