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drtio: fix master TSC KCSR readout

This commit is contained in:
Sebastien Bourdeauducq 2016-11-08 16:40:50 +08:00
parent 651d538217
commit bcb5053fb6
1 changed files with 1 additions and 1 deletions
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2
artiq/gateware/drtio/rt_controller.py
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@ -38,7 +38,7 @@ class RTController(Module):
# master RTIO counter and counter synchronization # master RTIO counter and counter synchronization
self.submodules.counter = RTIOCounter(64-fine_ts_width) self.submodules.counter = RTIOCounter(64-fine_ts_width)
self.sync += If(self.kcsrs.counter_update.re, self.sync += If(self.kcsrs.counter_update.re,
self.kcsrs.counter.status.eq(self.counter.value_sys)) self.kcsrs.counter.status.eq(self.counter.value_sys << fine_ts_width))
tsc_correction = Signal(64) tsc_correction = Signal(64)
self.csrs.tsc_correction.storage.attr.add("no_retiming") self.csrs.tsc_correction.storage.attr.add("no_retiming")
self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction) self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)