From bcb5053fb60ddba9a794762421faf1ee3c151d88 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 8 Nov 2016 16:40:50 +0800 Subject: [PATCH] drtio: fix master TSC KCSR readout --- artiq/gateware/drtio/rt_controller.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/rt_controller.py b/artiq/gateware/drtio/rt_controller.py index 4c4a95c27..e301443df 100644 --- a/artiq/gateware/drtio/rt_controller.py +++ b/artiq/gateware/drtio/rt_controller.py @@ -38,7 +38,7 @@ class RTController(Module): # master RTIO counter and counter synchronization self.submodules.counter = RTIOCounter(64-fine_ts_width) self.sync += If(self.kcsrs.counter_update.re, - self.kcsrs.counter.status.eq(self.counter.value_sys)) + self.kcsrs.counter.status.eq(self.counter.value_sys << fine_ts_width)) tsc_correction = Signal(64) self.csrs.tsc_correction.storage.attr.add("no_retiming") self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)