forked from M-Labs/artiq
drtio: check for absence of disparity errors before claiming RX ready
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4d07974a34
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@ -288,7 +288,7 @@ class LinkLayer(Module, AutoCSR):
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If(wait_scrambler.done,
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done_ps.i.eq(1),
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NextState("READY")
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),
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)
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)
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fsm.act("READY",
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If(reset_ps.o, NextState("RESET_RX"))
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@ -1,4 +1,6 @@
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from math import ceil
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from functools import reduce
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from operator import add
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from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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@ -134,7 +136,7 @@ class GTXInit(Module):
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# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
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# compared to the usual 8b10b binary representation.
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class BruteforceClockAligner(Module):
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def __init__(self, comma, rtio_clk_freq, check_period=6e-3, ready_time=50e-3):
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def __init__(self, comma, rtio_clk_freq, check_period=6e-3):
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self.rxdata = Signal(20)
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self.restart = Signal()
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@ -144,9 +146,12 @@ class BruteforceClockAligner(Module):
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check_max_val = ceil(check_period*rtio_clk_freq)
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check_counter = Signal(max=check_max_val+1)
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check = Signal()
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reset_check_counter = Signal()
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self.sync.rtio += [
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check.eq(0),
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If(~self.ready,
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If(reset_check_counter,
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check_counter.eq(check_max_val)
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).Else(
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If(check_counter == 0,
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check.eq(1),
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check_counter.eq(check_max_val)
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@ -156,37 +161,67 @@ class BruteforceClockAligner(Module):
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)
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]
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checks_reset = PulseSynchronizer("rtio", "rtio_rx")
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self.submodules += checks_reset
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comma_n = ~comma & 0b1111111111
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comma_seen_rxclk = Signal()
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comma_seen = Signal()
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comma_seen_rxclk.attr.add("no_retiming")
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self.specials += MultiReg(comma_seen_rxclk, comma_seen)
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comma_seen_reset = PulseSynchronizer("rtio", "rtio_rx")
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self.submodules += comma_seen_reset
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self.sync.rtio_rx += \
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If(comma_seen_reset.o,
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If(checks_reset.o,
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comma_seen_rxclk.eq(0)
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).Elif((self.rxdata[:10] == comma) | (self.rxdata[:10] == comma_n),
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comma_seen_rxclk.eq(1)
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)
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self.comb += \
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If(check,
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If(~comma_seen, self.restart.eq(1)),
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comma_seen_reset.i.eq(1)
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error_seen_rxclk = Signal()
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error_seen = Signal()
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error_seen_rxclk.attr.add("no_retiming")
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self.specials += MultiReg(error_seen_rxclk, error_seen)
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rx1cnt = Signal(max=11)
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self.sync.rtio_rx += [
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rx1cnt.eq(reduce(add, [self.rxdata[i] for i in range(10)])),
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If(checks_reset.o,
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error_seen_rxclk.eq(0)
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).Elif((rx1cnt != 4) & (rx1cnt != 5) & (rx1cnt != 6),
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error_seen_rxclk.eq(1)
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)
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ready_counts = ceil(ready_time/check_period)
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assert ready_counts > 1
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ready_counter = Signal(max=ready_counts+1, reset=ready_counts)
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self.sync.rtio += [
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If(check,
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If(comma_seen,
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If(ready_counter != 0, ready_counter.eq(ready_counter-1))
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).Else(
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ready_counter.eq(ready_counts)
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)
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),
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If(self.reset, ready_counter.eq(ready_counts))
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]
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self.comb += self.ready.eq(ready_counter == 0)
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fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="WAIT_COMMA"))
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self.submodules += fsm
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fsm.act("WAIT_COMMA",
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If(check,
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# Errors are still OK at this stage, as the transceiver
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# has just been reset and may output garbage data.
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If(comma_seen,
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NextState("WAIT_NOERROR")
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).Else(
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self.restart.eq(1)
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),
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checks_reset.i.eq(1)
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)
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)
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fsm.act("WAIT_NOERROR",
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If(check,
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If(comma_seen & ~error_seen,
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NextState("READY")
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).Else(
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self.restart.eq(1),
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NextState("WAIT_COMMA")
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),
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checks_reset.i.eq(1)
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)
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)
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fsm.act("READY",
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reset_check_counter.eq(1),
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self.ready.eq(1),
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If(self.reset,
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checks_reset.i.eq(1),
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self.restart.eq(1),
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NextState("WAIT_COMMA")
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)
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)
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