forked from M-Labs/artiq
drtio: reset link from CPU
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parent
f040e27041
commit
4d07974a34
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@ -3,7 +3,7 @@ from operator import xor, or_
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect.csr import *
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@ -223,10 +223,8 @@ class LinkLayerRX(Module):
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class LinkLayer(Module, AutoCSR):
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def __init__(self, encoder, decoders):
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self.link_status = CSRStatus()
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self.link_reset = CSR()
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# control signals, in rtio clock domain
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self.reset = Signal()
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self.ready = Signal()
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# pulsed to reset receiver, rx_ready must immediately go low
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self.rx_reset = Signal()
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# receiver locked including comma alignment
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@ -252,37 +250,46 @@ class LinkLayer(Module, AutoCSR):
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# # #
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ready_r = Signal()
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ready = Signal()
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reset_ps = PulseSynchronizer("sys", "rtio")
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done_ps = PulseSynchronizer("rtio", "sys")
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self.submodules += reset_ps, done_ps
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self.comb += reset_ps.i.eq(self.link_reset.re)
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self.sync += [
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If(done_ps.o, ready.eq(1)),
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If(reset_ps.i, ready.eq(0)),
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]
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self.comb += self.link_status.status.eq(ready)
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ready_rx = Signal()
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self.sync.rtio += ready_r.eq(self.ready)
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ready_r.attr.add("no_retiming")
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self.specials += MultiReg(ready_r, ready_rx, "rtio_rx")
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ready.attr.add("no_retiming")
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self.specials += MultiReg(ready, ready_rx, "rtio_rx")
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self.comb += [
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self.rx_aux_frame.eq(rx.aux_frame & ready_rx),
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self.rx_rt_frame.eq(rx.rt_frame & ready_rx),
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]
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self.specials += MultiReg(ready_r, self.link_status.status)
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wait_scrambler = WaitTimer(15)
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wait_scrambler = ClockDomainsRenamer("rtio")(WaitTimer(15))
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self.submodules += wait_scrambler
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fsm = ClockDomainsRenamer("rtio")(
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ResetInserter()(FSM(reset_state="RESET_RX")))
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fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="RESET_RX"))
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self.submodules += fsm
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self.comb += fsm.reset.eq(self.reset)
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fsm.act("RESET_RX",
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self.rx_reset.eq(1),
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NextState("WAIT_RX_READY")
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)
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fsm.act("WAIT_RX_READY",
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If(self.rx_ready, NextState("WAIT_SCRAMBLER_SYNC"))
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If(self.rx_ready, NextState("WAIT_SCRAMBLER_SYNC")),
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If(reset_ps.o, NextState("RESET_RX"))
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)
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fsm.act("WAIT_SCRAMBLER_SYNC",
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wait_scrambler.wait.eq(1),
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If(wait_scrambler.done, NextState("READY")),
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If(wait_scrambler.done,
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done_ps.i.eq(1),
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NextState("READY")
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),
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)
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fsm.act("READY",
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self.ready.eq(1)
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If(reset_ps.o, NextState("RESET_RX"))
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)
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@ -7,6 +7,12 @@ fn drtio_link_is_up() -> bool {
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}
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}
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fn drtio_reset_link() {
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unsafe {
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csr::drtio::link_reset_write(1)
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}
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}
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fn drtio_sync_tsc() {
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unsafe {
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csr::drtio::set_time_write(1);
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@ -33,7 +39,7 @@ pub fn link_thread(waiter: Waiter, _spawner: Spawner) {
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waiter.until(drtio_link_is_up).unwrap();
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info!("link RX is up");
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waiter.sleep(300);
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waiter.sleep(300).unwrap();
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info!("wait for remote side done");
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drtio_sync_tsc();
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@ -48,23 +54,24 @@ pub fn link_thread(waiter: Waiter, _spawner: Spawner) {
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}
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}
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fn drtio_error_present() -> bool {
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fn drtio_packet_error_present() -> bool {
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unsafe {
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csr::drtio::err_present_read() != 0
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csr::drtio::packet_err_present_read() != 0
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}
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}
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fn drtio_get_error() -> u8 {
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fn drtio_get_packet_error() -> u8 {
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unsafe {
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let err = csr::drtio::err_code_read();
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csr::drtio::err_present_write(1);
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let err = csr::drtio::packet_err_code_read();
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csr::drtio::packet_err_present_write(1);
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err
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}
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}
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pub fn error_thread(waiter: Waiter, _spawner: Spawner) {
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loop {
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waiter.until(drtio_error_present).unwrap();
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error!("DRTIO error {}", drtio_get_error());
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waiter.until(drtio_packet_error_present).unwrap();
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error!("DRTIO packet error {}", drtio_get_packet_error());
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drtio_reset_link();
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}
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}
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