forked from M-Labs/artiq
phaser: doc tweaks
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@ -76,8 +76,9 @@ class Phaser:
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The four 16 bit 500 MS/s DAC data streams are sent via a 32 bit parallel
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LVDS bus operating at 1 Gb/s per pin pair and processed in the DAC. On the
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DAC 2x interpolation, sinx/x compensation, quadrature modulator compensation,
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fine and coarse mixing as well as group delay capabilities are available.
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DAC 2x interpolation, sinx/x compensation, quadrature modulator
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compensation, fine and coarse mixing as well as group delay capabilities
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are available.
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The latency/group delay from the RTIO events setting
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:class:`PhaserOscillator` or :class:`PhaserChannel` DUC parameters all they
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@ -97,16 +98,19 @@ class Phaser:
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31.5 dB range step attenuator and is available at the front panel.
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The DAC, the analog quadrature upconverters and the two attenuators are
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configured through a shared SPI bus that is accessed and controlled via FPGA
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registers.
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configured through a shared SPI bus that is accessed and controlled via
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FPGA registers.
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:param channel: Base RTIO channel number
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:param core_device: Core device name (default: "core")
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:param miso_delay: Fastlink MISO signal delay to account for cable
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and buffer round trip. This might be automated later.
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:attr:`channel`: List of two :class:`PhaserChannel` to access oscillators
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and digital upconverter.
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Attributes:
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* :attr:`channel`: List of two :class:`PhaserChannel`
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To access oscillators, digital upconverters, PLL/VCO analog
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quadrature upconverters and attenuators.
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"""
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kernel_invariants = {"core", "channel_base", "t_frame", "miso_delay"}
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@ -185,7 +189,7 @@ class Phaser:
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def set_fan_mu(self, pwm):
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"""Set the fan duty cycle.
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:param pwm: Duty cycle (8 bit)
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:param pwm: Duty cycle in machine units (8 bit)
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"""
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self.write8(PHASER_ADDR_FAN, pwm)
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@ -228,13 +232,13 @@ class Phaser:
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Bit flags are:
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* `PHASER_STA_DAC_ALARM`: DAC alarm pin
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* `PHASER_STA_TRF0_LD`: Quadrature upconverter 0 lock detect
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* `PHASER_STA_TRF1_LD`: Quadrature upconverter 1 lock detect
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* `PHASER_STA_TERM0`: ADC channel 0 termination indicator
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* `PHASER_STA_TERM1`: ADC channel 1 termination indicator
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* `PHASER_STA_SPI_IDLE`: SPI machine is idle and data registers can be
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read/written
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* :const:`PHASER_STA_DAC_ALARM`: DAC alarm pin
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* :const:`PHASER_STA_TRF0_LD`: Quadrature upconverter 0 lock detect
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* :const:`PHASER_STA_TRF1_LD`: Quadrature upconverter 1 lock detect
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* :const:`PHASER_STA_TERM0`: ADC channel 0 termination indicator
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* :const:`PHASER_STA_TERM1`: ADC channel 1 termination indicator
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* :const:`PHASER_STA_SPI_IDLE`: SPI machine is idle and data registers
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can be read/written
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:return: Status register
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"""
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@ -339,7 +343,9 @@ class Phaser:
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class PhaserChannel:
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"""Phaser channel IQ pair.
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:attr:`oscillator`: List of five :class:`PhaserOscillator`.
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Attributes:
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* :attr:`oscillator`: List of five :class:`PhaserOscillator`.
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.. note:: The amplitude sum of the oscillators must be less than one to
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avoid clipping or overflow. If any of the DDS or DUC frequencies are
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@ -433,7 +439,7 @@ class PhaserChannel:
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def set_att_mu(self, data):
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"""Set channel attenuation.
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:param data: Attenuator data
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:param data: Attenuator data in machine units (8 bit)
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"""
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div = 34 # 30 ns min period
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t_xfer = self.phaser.core.seconds_to_mu((8 + 1)*div*4*ns)
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@ -448,6 +454,7 @@ class PhaserChannel:
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:param att: Attenuation in dB
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"""
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# 2 lsb are inactive, resulting in 8 LSB per dB
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data = 0xff - int32(round(att*8))
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if data < 0 or data > 0xff:
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raise ValueError("invalid attenuation")
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