forked from M-Labs/artiq
587 lines
20 KiB
Python
587 lines
20 KiB
Python
from artiq.language.core import kernel, delay_mu, delay
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.language.units import us, ns, MHz
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from artiq.language.types import TInt32
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PHASER_BOARD_ID = 19
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PHASER_ADDR_BOARD_ID = 0x00
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PHASER_ADDR_HW_REV = 0x01
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PHASER_ADDR_GW_REV = 0x02
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PHASER_ADDR_CFG = 0x03
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PHASER_ADDR_STA = 0x04
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PHASER_ADDR_CRC_ERR = 0x05
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PHASER_ADDR_LED = 0x06
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PHASER_ADDR_FAN = 0x07
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PHASER_ADDR_DUC_STB = 0x08
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PHASER_ADDR_ADC_CFG = 0x09
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PHASER_ADDR_SPI_CFG = 0x0a
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PHASER_ADDR_SPI_DIVLEN = 0x0b
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PHASER_ADDR_SPI_SEL = 0x0c
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PHASER_ADDR_SPI_DATW = 0x0d
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PHASER_ADDR_SPI_DATR = 0x0e
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# PHASER_ADDR_RESERVED0 = 0x0f
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PHASER_ADDR_DUC0_CFG = 0x10
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# PHASER_ADDR_DUC0_RESERVED0 = 0x11
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PHASER_ADDR_DUC0_F = 0x12
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PHASER_ADDR_DUC0_P = 0x16
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PHASER_ADDR_DAC0_DATA = 0x18
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PHASER_ADDR_DAC0_TEST = 0x1c
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PHASER_ADDR_DUC1_CFG = 0x20
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# PHASER_ADDR_DUC1_RESERVED0 = 0x21
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PHASER_ADDR_DUC1_F = 0x22
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PHASER_ADDR_DUC1_P = 0x26
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PHASER_ADDR_DAC1_DATA = 0x28
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PHASER_ADDR_DAC1_TEST = 0x2c
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PHASER_SEL_DAC = 1 << 0
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PHASER_SEL_TRF0 = 1 << 1
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PHASER_SEL_TRF1 = 1 << 2
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PHASER_SEL_ATT0 = 1 << 3
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PHASER_SEL_ATT1 = 1 << 4
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PHASER_STA_DAC_ALARM = 1 << 0
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PHASER_STA_TRF0_LD = 1 << 1
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PHASER_STA_TRF1_LD = 1 << 2
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PHASER_STA_TERM0 = 1 << 3
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PHASER_STA_TERM1 = 1 << 4
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PHASER_STA_SPI_IDLE = 1 << 5
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PHASER_DAC_SEL_DUC = 0
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PHASER_DAC_SEL_TEST = 1
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class Phaser:
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"""Phaser 4-channel, 16-bit, 1 GS/s DAC coredevice driver.
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Phaser contains a 4 channel, 1 GS/s DAC chip with integrated upconversion,
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quadrature modulation compensation and interpolation features.
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The coredevice produces 2 IQ data streams with 25 MS/s and 14 bit per
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quadrature. Each data stream supports 5 independent numerically controlled
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IQ oscillators (NCOs, DDSs with 32 bit frequency, 16 bit phase, 15 bit
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amplitude, and phase accumulator clear functionality) added together.
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See :class:`PhaserChannel` and :class:`PhaserOscillator`.
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Together with a data clock, framing marker, a checksum and metadata for
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register access the streams are sent in groups of 8 samples over 1.5 Gb/s
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FastLink via a single EEM connector from coredevice to Phaser.
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On Phaser in the FPGA the data streams are buffered and interpolated
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from 25 MS/s to 500 MS/s 16 bit followed by a 500 MS/s digital upconverter
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with adjustable frequency and phase. The interpolation passband is 20 MHz
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wide, passband ripple is less than 1e-3 amplitude, stopband attenuation
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is better than 75 dB at offsets > 15 MHz and better than 90 dB at offsets
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> 30 MHz.
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The four 16 bit 500 MS/s DAC data streams are sent via a 32 bit parallel
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LVDS bus operating at 1 Gb/s per pin pair and processed in the DAC. On the
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DAC 2x interpolation, sinx/x compensation, quadrature modulator
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compensation, fine and coarse mixing as well as group delay capabilities
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are available.
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The latency/group delay from the RTIO events setting
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:class:`PhaserOscillator` or :class:`PhaserChannel` DUC parameters all they
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way to the DAC outputs is deterministic. This enables deterministic
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absolute phase with respect to other RTIO input and output events.
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The four analog DAC outputs are passed through anti-aliasing filters.
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In the baseband variant, the even/in-phase DAC channels feed 31.5 dB range
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attenuators and are available on the front panel. The odd outputs are
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available at MMCX connectors on board.
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In the upconverter variant, each of the two IQ (in-phase and quadrature)
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output pairs feeds a one quadrature upconverter with integrated PLL/VCO.
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This analog quadrature upconverter supports offset tuning for carrier and
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sideband suppression. The output from the upconverter passes through the
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31.5 dB range step attenuator and is available at the front panel.
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The DAC, the analog quadrature upconverters and the two attenuators are
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configured through a shared SPI bus that is accessed and controlled via
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FPGA registers.
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:param channel: Base RTIO channel number
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:param core_device: Core device name (default: "core")
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:param miso_delay: Fastlink MISO signal delay to account for cable
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and buffer round trip. This might be automated later.
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Attributes:
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* :attr:`channel`: List of two :class:`PhaserChannel`
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To access oscillators, digital upconverters, PLL/VCO analog
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quadrature upconverters and attenuators.
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"""
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kernel_invariants = {"core", "channel_base", "t_frame", "miso_delay"}
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def __init__(self, dmgr, channel_base, miso_delay=1, core_device="core"):
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self.channel_base = channel_base
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self.core = dmgr.get(core_device)
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# TODO: auto-align miso-delay in phy
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self.miso_delay = miso_delay
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# frame duration in mu (10 words, 8 clock cycles each 4 ns)
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# self.core.seconds_to_mu(10*8*4*ns) # unfortunately this returns 319
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assert self.core.ref_period == 1*ns
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self.t_frame = 10*8*4
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self.channel = [PhaserChannel(self, ch) for ch in range(2)]
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@kernel
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def init(self):
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"""Initialize the board.
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Verifies board presence by reading the board ID register.
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Does not alter any state.
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"""
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board_id = self.read8(PHASER_ADDR_BOARD_ID)
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if board_id != PHASER_BOARD_ID:
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raise ValueError("invalid board id")
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delay(20*us) # slack
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@kernel
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def write8(self, addr, data):
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"""Write data to FPGA register.
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:param addr: Address to write to (7 bit)
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:param data: Data to write (8 bit)
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"""
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rtio_output((self.channel_base << 8) | (addr & 0x7f) | 0x80, data)
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delay_mu(int64(self.t_frame))
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@kernel
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def read8(self, addr) -> TInt32:
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"""Read from FPGA register.
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:param addr: Address to read from (7 bit)
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:return: Data read (8 bit)
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"""
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rtio_output((self.channel_base << 8) | (addr & 0x7f), 0)
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response = rtio_input_data(self.channel_base)
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return response >> self.miso_delay
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@kernel
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def write32(self, addr, data: TInt32):
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"""Write 32 bit to a sequence of FPGA registers."""
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for offset in range(4):
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byte = data >> 24
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self.write8(addr + offset, byte)
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data <<= 8
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@kernel
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def read32(self, addr) -> TInt32:
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"""Read 32 bit from a sequence of FPGA registers."""
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data = 0
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for offset in range(4):
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data <<= 8
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data |= self.read8(addr + offset)
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delay(20*us) # slack
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return data
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@kernel
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def set_leds(self, leds):
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"""Set the front panel LEDs.
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:param leds: LED settings (6 bit)
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"""
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self.write8(PHASER_ADDR_LED, leds)
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@kernel
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def set_fan_mu(self, pwm):
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"""Set the fan duty cycle.
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:param pwm: Duty cycle in machine units (8 bit)
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"""
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self.write8(PHASER_ADDR_FAN, pwm)
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@kernel
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def set_fan(self, duty):
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"""Set the fan duty cycle.
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:param duty: Duty cycle (0. to 1.)
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"""
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pwm = int32(round(duty*255.))
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if pwm < 0 or pwm > 255:
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raise ValueError("invalid duty cycle")
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self.set_fan_mu(pwm)
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@kernel
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def set_cfg(self, clk_sel=0, dac_resetb=1, dac_sleep=0, dac_txena=1,
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trf0_ps=0, trf1_ps=0, att0_rstn=1, att1_rstn=1):
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"""Set the configuration register.
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Each flag is a single bit (0 or 1).
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:param clk_sel: Select the external SMA clock input
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:param dac_resetb: Active low DAC reset pin
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:param dac_sleep: DAC sleep pin
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:param dac_txena: Enable DAC transmission pin
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:param trf0_ps: Quadrature upconverter 0 power save
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:param trf1_ps: Quadrature upconverter 1 power save
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:param att0_rstn: Active low attenuator 0 reset
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:param att1_rstn: Active low attenuator 1 reset
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"""
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self.write8(PHASER_ADDR_CFG,
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((clk_sel & 1) << 0) | ((dac_resetb & 1) << 1) |
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((dac_sleep & 1) << 2) | ((dac_txena & 1) << 3) |
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((trf0_ps & 1) << 4) | ((trf1_ps & 1) << 5) |
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((att0_rstn & 1) << 6) | ((att1_rstn & 1) << 7))
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@kernel
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def get_sta(self):
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"""Get the status register value.
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Bit flags are:
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* :const:`PHASER_STA_DAC_ALARM`: DAC alarm pin
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* :const:`PHASER_STA_TRF0_LD`: Quadrature upconverter 0 lock detect
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* :const:`PHASER_STA_TRF1_LD`: Quadrature upconverter 1 lock detect
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* :const:`PHASER_STA_TERM0`: ADC channel 0 termination indicator
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* :const:`PHASER_STA_TERM1`: ADC channel 1 termination indicator
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* :const:`PHASER_STA_SPI_IDLE`: SPI machine is idle and data registers
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can be read/written
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:return: Status register
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"""
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return self.read8(PHASER_ADDR_STA)
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@kernel
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def get_crc_err(self):
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"""Get the frame CRC error counter.
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:return: The number of frames with CRC mismatches sind the reset of the
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device. Overflows at 256.
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"""
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return self.read8(PHASER_ADDR_CRC_ERR)
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@kernel
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def duc_stb(self):
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"""Strobe the DUC configuration register update.
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Transfer staging to active registers.
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This affects both DUC channels.
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"""
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self.write8(PHASER_ADDR_DUC_STB, 0)
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@kernel
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def spi_cfg(self, select, div, end, clk_phase=0, clk_polarity=0,
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half_duplex=0, lsb_first=0, offline=0, length=8):
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"""Set the SPI machine configuration
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:param select: Chip selects to assert (DAC, TRF0, TRF1, ATT0, ATT1)
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:param div: SPI clock divider relative to 250 MHz fabric clock
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:param end: Whether to end the SPI transaction and deassert chip select
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:param clk_phase: SPI clock phase (sample on first or second edge)
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:param clk_polarity: SPI clock polarity (idle low or high)
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:param half_duplex: Read MISO data from MOSI wire
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:param lsb_first: Transfer the least significant bit first
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:param offline: Put the SPI interfaces offline and don't drive voltages
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:param length: SPI transfer length (1 to 8 bits)
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"""
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if div < 2 or div > 257:
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raise ValueError("invalid divider")
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if length < 1 or length > 8:
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raise ValueError("invalid length")
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self.write8(PHASER_ADDR_SPI_SEL, select)
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self.write8(PHASER_ADDR_SPI_DIVLEN, (div - 2 >> 3) | (length - 1 << 5))
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self.write8(PHASER_ADDR_SPI_CFG,
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((offline & 1) << 0) | ((end & 1) << 1) |
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((clk_phase & 1) << 2) | ((clk_polarity & 1) << 3) |
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((half_duplex & 1) << 4) | ((lsb_first & 1) << 5))
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@kernel
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def spi_write(self, data):
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"""Write 8 bits into the SPI data register and start/continue the
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transaction."""
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self.write8(PHASER_ADDR_SPI_DATW, data)
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@kernel
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def spi_read(self):
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"""Read from the SPI input data register."""
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return self.read8(PHASER_ADDR_SPI_DATR)
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@kernel
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def dac_write(self, addr, data):
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"""Write 16 bit to a DAC register.
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:param addr: Register address
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:param data: Register data to write
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"""
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div = 34 # 100 ns min period
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.spi_cfg(select=PHASER_SEL_DAC, div=div, end=0)
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self.spi_write(addr)
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delay_mu(t_xfer)
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self.spi_write(data >> 8)
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delay_mu(t_xfer)
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self.spi_cfg(select=PHASER_SEL_DAC, div=div, end=1)
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self.spi_write(data)
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delay_mu(t_xfer)
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@kernel
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def dac_read(self, addr, div=34) -> TInt32:
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"""Read from a DAC register.
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:param addr: Register address to read from
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:param div: SPI clock divider. Needs to be at least 250 (1 µs SPI
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clock) to read the temperature register.
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"""
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t_xfer = self.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.spi_cfg(select=PHASER_SEL_DAC, div=div, end=0)
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self.spi_write(addr | 0x80)
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delay_mu(t_xfer)
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self.spi_write(0)
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delay_mu(t_xfer)
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data = self.spi_read() << 8
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delay(20*us) # slack
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self.spi_cfg(select=PHASER_SEL_DAC, div=div, end=1)
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self.spi_write(0)
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delay_mu(t_xfer)
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data |= self.spi_read()
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return data
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class PhaserChannel:
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"""Phaser channel IQ pair.
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Attributes:
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* :attr:`oscillator`: List of five :class:`PhaserOscillator`.
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.. note:: The amplitude sum of the oscillators must be less than one to
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avoid clipping or overflow. If any of the DDS or DUC frequencies are
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non-zero, it is not sufficient to ensure that the sum in each
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quadrature is within range.
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.. note:: The interpolation filter on Phaser has an intrinsic sinc-like
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overshoot in its step response. That overshoot is an direct consequence
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of its near-brick-wall frequency response. For large and wide-band
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changes in oscillator parameters, the overshoot can lead to clipping
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or overflow after the interpolation. Either band-limit any changes
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in the oscillator parameters or back off the amplitude sufficiently.
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"""
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kernel_invariants = {"index", "phaser"}
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def __init__(self, phaser, index):
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self.phaser = phaser
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self.index = index
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self.oscillator = [PhaserOscillator(self, osc) for osc in range(5)]
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@kernel
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def get_dac_data(self) -> TInt32:
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"""Get a sample of the current DAC data.
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The data is split accross multiple registers and thus the data
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is only valid if constant.
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:return: DAC data as 32 bit IQ. I in the 16 LSB, Q in the 16 MSB
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"""
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return self.phaser.read32(PHASER_ADDR_DAC0_DATA + (self.index << 4))
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@kernel
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def set_dac_test(self, data: TInt32):
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"""Set the DAC test data.
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:param data: 32 bit IQ test data, I in the 16 LSB, Q in the 16 MSB
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"""
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self.phaser.write32(PHASER_ADDR_DAC0_TEST + (self.index << 4), data)
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@kernel
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def set_duc_cfg(self, clr=0, clr_once=0, select=0):
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"""Set the digital upconverter and interpolator configuration.
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:param clr: Keep the phase accumulator cleared (persistent)
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:param clr_once: Clear the phase accumulator for one cycle
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:param select: Select the data to send to the DAC (0: DUC data, 1: test
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data, other values: reserved)
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"""
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self.phaser.write8(PHASER_ADDR_DUC0_CFG + (self.index << 4),
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((clr & 1) << 0) | ((clr_once & 1) << 1) |
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((select & 3) << 2))
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@kernel
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def set_duc_frequency_mu(self, ftw):
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"""Set the DUC frequency.
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:param ftw: DUC frequency tuning word (32 bit)
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"""
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self.phaser.write32(PHASER_ADDR_DUC0_F + (self.index << 4), ftw)
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@kernel
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def set_duc_frequency(self, frequency):
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"""Set the DUC frequency.
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:param frequency: DUC frequency in Hz (passband from -200 MHz to
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200 MHz, wrapping around at +- 250 MHz)
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"""
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ftw = int32(round(frequency*((1 << 32)/(500*MHz))))
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self.set_duc_frequency_mu(ftw)
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@kernel
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def set_duc_phase_mu(self, pow):
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"""Set the DUC phase offset
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:param pow: DUC phase offset word (16 bit)
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"""
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addr = PHASER_ADDR_DUC0_P + (self.index << 4)
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self.phaser.write8(addr, pow >> 8)
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self.phaser.write8(addr + 1, pow)
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@kernel
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def set_duc_phase(self, phase):
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"""Set the DUC phase.
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:param phase: DUC phase in turns
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"""
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pow = int32(round(phase*(1 << 16)))
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self.set_duc_phase_mu(pow)
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@kernel
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def set_att_mu(self, data):
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"""Set channel attenuation.
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:param data: Attenuator data in machine units (8 bit)
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"""
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div = 34 # 30 ns min period
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t_xfer = self.phaser.core.seconds_to_mu((8 + 1)*div*4*ns)
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self.phaser.spi_cfg(select=PHASER_SEL_ATT0 << self.index, div=div,
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end=1)
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self.phaser.spi_write(data)
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delay_mu(t_xfer)
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@kernel
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def set_att(self, att):
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"""Set channel attenuation in SI units.
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:param att: Attenuation in dB
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"""
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# 2 lsb are inactive, resulting in 8 LSB per dB
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data = 0xff - int32(round(att*8))
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if data < 0 or data > 0xff:
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raise ValueError("invalid attenuation")
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self.set_att_mu(data)
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@kernel
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def get_att_mu(self) -> TInt32:
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"""Read current attenuation.
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The current attenuation value is read without side effects.
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:return: Current attenuation in machine units
|
|
"""
|
|
div = 34
|
|
t_xfer = self.phaser.core.seconds_to_mu((8 + 1)*div*4*ns)
|
|
self.phaser.spi_cfg(select=PHASER_SEL_ATT0 << self.index, div=div,
|
|
end=0)
|
|
self.phaser.spi_write(0)
|
|
delay_mu(t_xfer)
|
|
data = self.phaser.spi_read()
|
|
delay(20*us) # slack
|
|
self.phaser.spi_cfg(select=PHASER_SEL_ATT0 << self.index, div=div,
|
|
end=1)
|
|
self.phaser.spi_write(data)
|
|
delay_mu(t_xfer)
|
|
return data
|
|
|
|
@kernel
|
|
def trf_write(self, data, readback=False):
|
|
"""Write 32 bits to upconverter.
|
|
|
|
:param data: Register data (32 bit) containing encoded address
|
|
:param readback: Whether to return the read back MISO data
|
|
"""
|
|
div = 34 # 50 ns min period
|
|
t_xfer = self.phaser.core.seconds_to_mu((8 + 1)*div*4*ns)
|
|
read = 0
|
|
end = 0
|
|
clk_phase = 0
|
|
if readback:
|
|
clk_phase = 1
|
|
for i in range(4):
|
|
if i == 0 or i == 3:
|
|
if i == 3:
|
|
end = 1
|
|
self.phaser.spi_cfg(select=PHASER_SEL_TRF0 << self.index,
|
|
div=div, lsb_first=1, clk_phase=clk_phase,
|
|
end=end)
|
|
self.phaser.spi_write(data)
|
|
data >>= 8
|
|
delay_mu(t_xfer)
|
|
if readback:
|
|
read >>= 8
|
|
read |= self.phaser.spi_read() << 24
|
|
delay(20*us) # slack
|
|
return read
|
|
|
|
@kernel
|
|
def trf_read(self, addr, cnt_mux_sel=0) -> TInt32:
|
|
"""Quadrature upconverter register read.
|
|
|
|
:param addr: Register address to read (0 to 7)
|
|
:param cnt_mux_sel: Report VCO counter min or max frequency
|
|
:return: Register data (32 bit)
|
|
"""
|
|
self.trf_write(0x80000008 | (addr << 28) | (cnt_mux_sel << 27))
|
|
# single clk pulse with ~LE to start readback
|
|
self.phaser.spi_cfg(select=0, div=34, end=1, length=1)
|
|
self.phaser.spi_write(0)
|
|
delay((1 + 1)*34*4*ns)
|
|
return self.trf_write(0x00000008, readback=True)
|
|
|
|
|
|
class PhaserOscillator:
|
|
"""Phaser IQ channel oscillator (NCO/DDS).
|
|
|
|
.. note:: Latencies between oscillators within a channel and between
|
|
oscillator paramters (amplitude and phase/frequency) are deterministic
|
|
(with respect to the 25 MS/s sample clock) but not matched.
|
|
"""
|
|
kernel_invariants = {"channel", "base_addr"}
|
|
|
|
def __init__(self, channel, index):
|
|
self.channel = channel
|
|
self.base_addr = ((self.channel.phaser.channel_base + 1 +
|
|
self.channel.index) << 8) | (index << 1)
|
|
|
|
@kernel
|
|
def set_frequency_mu(self, ftw):
|
|
"""Set Phaser MultiDDS frequency tuning word.
|
|
|
|
:param ftw: Frequency tuning word (32 bit)
|
|
"""
|
|
rtio_output(self.base_addr, ftw)
|
|
|
|
@kernel
|
|
def set_frequency(self, frequency):
|
|
"""Set Phaser MultiDDS frequency.
|
|
|
|
:param frequency: Frequency in Hz (passband from -10 MHz to 10 MHz,
|
|
wrapping around at +- 12.5 MHz)
|
|
"""
|
|
ftw = int32(round(frequency*((1 << 32)/(25*MHz))))
|
|
self.set_frequency_mu(ftw)
|
|
|
|
@kernel
|
|
def set_amplitude_phase_mu(self, asf=0x7fff, pow=0, clr=0):
|
|
"""Set Phaser MultiDDS amplitude, phase offset and accumulator clear.
|
|
|
|
:param asf: Amplitude (15 bit)
|
|
:param pow: Phase offset word (16 bit)
|
|
:param clr: Clear the phase accumulator (persistent)
|
|
"""
|
|
data = (asf & 0x7fff) | ((clr & 1) << 15) | (pow << 16)
|
|
rtio_output(self.base_addr | 1, data)
|
|
|
|
@kernel
|
|
def set_amplitude_phase(self, amplitude, phase=0., clr=0):
|
|
"""Set Phaser MultiDDS amplitude and phase.
|
|
|
|
:param amplitude: Amplitude in units of full scale
|
|
:param phase: Phase in turns
|
|
:param clr: Clear the phase accumulator (persistent)
|
|
"""
|
|
asf = int32(round(amplitude*0x7fff))
|
|
if asf < 0 or asf > 0x7fff:
|
|
raise ValueError("invalid amplitude")
|
|
pow = int32(round(phase*(1 << 16)))
|
|
self.set_amplitude_phase_mu(asf, pow, clr)
|