srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma: add sysref sampler to DRTIO master

This commit is contained in:
Sebastien Bourdeauducq 2018-06-21 22:28:34 +08:00
parent 07bcdfd91e
commit b28ff587c5
1 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/gateware/targets/sayma_amc.py
View File

@ -309,6 +309,12 @@ class Master(MiniSoC, AMPSoC, RTMCommon):
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.submodules.ad9154_crg = jesd204_tools.UltrascaleCRG(platform)
self.csr_devices.append("ad9154_crg")
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.ad9154_crg.cd_jesd.clk)
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
@ -325,6 +331,10 @@ class Master(MiniSoC, AMPSoC, RTMCommon):
[self.rtio_core.cri] + drtio_cri)
self.register_kernel_cpu_csrdevice("cri_con")
self.submodules.sysref_sampler = jesd204_tools.SysrefSampler(
self.rtio_core.coarse_ts, self.ad9154_crg.jref)
self.csr_devices.append("sysref_sampler")
class Satellite(BaseSoC, RTMCommon):
mem_map = {