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sayma: remove with_sawg from Master variant

This commit is contained in:
Sebastien Bourdeauducq 2018-07-15 17:38:29 +08:00
parent 123e7bc054
commit b2695d03ed
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/targets/sayma_amc.py
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@ -379,7 +379,7 @@ class Master(MiniSoC, AMPSoC):
} }
mem_map.update(MiniSoC.mem_map) mem_map.update(MiniSoC.mem_map)
def __init__(self, with_sawg, **kwargs): def __init__(self, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type="or1k", cpu_type="or1k",
sdram_controller_type="minicon", sdram_controller_type="minicon",
@ -624,7 +624,7 @@ def main():
elif variant == "masterdac": elif variant == "masterdac":
cls = MasterDAC cls = MasterDAC
elif variant == "master": elif variant == "master":
cls = Master cls = lambda dummy_with_sawg, **kwargs: Master(**kwargs)
elif variant == "satellite": elif variant == "satellite":
cls = Satellite cls = Satellite
else: else: