forked from M-Labs/artiq
sayma: remove with_sawg from Master variant
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123e7bc054
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b2695d03ed
@ -379,7 +379,7 @@ class Master(MiniSoC, AMPSoC):
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, with_sawg, **kwargs):
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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@ -624,7 +624,7 @@ def main():
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elif variant == "masterdac":
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cls = MasterDAC
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elif variant == "master":
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cls = Master
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cls = lambda dummy_with_sawg, **kwargs: Master(**kwargs)
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elif variant == "satellite":
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cls = Satellite
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else:
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