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phaser: use new jesd clocking

This commit is contained in:
Florent Kermarrec 2016-10-13 11:51:06 +02:00
parent 81511feab8
commit af0e8582a2
1 changed files with 7 additions and 4 deletions
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11
artiq/gateware/targets/kc705.py
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@ -466,10 +466,13 @@ class AD9154(Module, AutoCSR):
rtio_freq = 125*1000*1000 rtio_freq = 125*1000*1000
jesd_qpll = GTXQuadPLL( jesd_qpll = GTXQuadPLL(
rtio_crg.refclk, jesd_refclk_freq, jesd_linerate) rtio_crg.refclk, jesd_refclk_freq, jesd_linerate)
jesd_phys = [JESD204BPhyTX( self.submodules += jesd_qpll
jesd_qpll, platform.request("ad9154_jesd", i), jesd_phys = []
rtio_freq, i) for i in range(4)] for i in range(4):
self.submodules += jesd_qpll, jesd_phys jesd_phy = [JESD204BPhyTX(jesd_qpll,
platform.request("ad9154_jesd", i), rtio_freq)
jesd_phys.append(jesd_phy)
setattr(self.submodules, "jesd_phy"+str(i), jesd_phy)
for jesd_phy in jesd_phys: for jesd_phy in jesd_phys:
platform.add_period_constraint( platform.add_period_constraint(
jesd_phy.gtx.cd_tx.clk, jesd_phy.gtx.cd_tx.clk,