From af0e8582a231beb2a09f716196eeb7bbda86a07e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 13 Oct 2016 11:51:06 +0200 Subject: [PATCH] phaser: use new jesd clocking --- artiq/gateware/targets/kc705.py | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 749cc6c20..0684ebd29 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -466,10 +466,13 @@ class AD9154(Module, AutoCSR): rtio_freq = 125*1000*1000 jesd_qpll = GTXQuadPLL( rtio_crg.refclk, jesd_refclk_freq, jesd_linerate) - jesd_phys = [JESD204BPhyTX( - jesd_qpll, platform.request("ad9154_jesd", i), - rtio_freq, i) for i in range(4)] - self.submodules += jesd_qpll, jesd_phys + self.submodules += jesd_qpll + jesd_phys = [] + for i in range(4): + jesd_phy = [JESD204BPhyTX(jesd_qpll, + platform.request("ad9154_jesd", i), rtio_freq) + jesd_phys.append(jesd_phy) + setattr(self.submodules, "jesd_phy"+str(i), jesd_phy) for jesd_phy in jesd_phys: platform.add_period_constraint( jesd_phy.gtx.cd_tx.clk,