forked from M-Labs/artiq
gateware: use default MiSoC timer
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@ -10,19 +10,13 @@ from artiq import __artiq_dir__ as artiq_dir
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class AMPSoC:
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"""Contains timer, kernel CPU and mailbox for ARTIQ SoCs.
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"""Contains kernel CPU and mailbox for ARTIQ SoCs.
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Users must disable the timer from the platform SoC and provide
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a "mailbox" entry in the memory map.
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Users must provide a "mailbox" entry in the memory map.
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"""
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def __init__(self):
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if not hasattr(self, "cpu"):
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raise ValueError("Platform SoC must be initialized first")
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if hasattr(self, "timer0"):
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raise ValueError("Timer already exists. "
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"Initialize platform SoC using with_timer=False")
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self.submodules.timer0 = timer.Timer(width=64)
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self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
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self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
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